Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
1999-09-07
2001-07-03
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
C438S158000, C438S159000
Reexamination Certificate
active
06255130
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a thin film transistor array panel and a method for manufacturing the same, especially to a method for manufacturing a thin film transistor array panel with less number of photolithography steps.
(b) Description of the Related Art
A liquid crystal display (LCD) is one of the most popular flat panel displays (FPDs). An LCD has two panels having electrodes for generating electric fields and a liquid crystal layer interposed therebetween.
The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
In the most widely used liquid crystal display, the field-generating electrodes are formed at each of the two panels, and one of the panels has switching elements such as thin film transistors.
In general, a thin film transistor array panel is manufactured by photolithography using a plurality of photomasks, and five or six photolithography steps are used. Since the photolithography process is expensive, it is desirable to reduce the number of the photolithography steps. Even though manufacturing methods using only four photolithography steps have been suggested, these methods are not easy to accomplish.
A conventional method for manufacturing a thin film transistor array panel using four photolithography steps is disclosed in U.S. Pat. No. 5,478,766 and will now be described.
First, a gate wire of aluminum or aluminum alloy is formed on a substrate using a first mask. Then, a gate insulating layer, an amorphous silicon layer, an n+ amorphous silicon layer, and a metal layer are sequentially deposited. The metal layer, the n+ amorphous silicon, and the amorphous silicon layer are patterned by using a second mask. At this time, gate pads of the gate wire are covered only with the gate insulating layer. An indium tin oxide (ITO) is deposited and patterned by using a third mask. Then the portions of the ITO layer over the gate pads are removed. After the metal layer and the underlying n+ amorphous silicon layer are patterned using the patterned ITO layer as etch mask, a passivation layer is deposited. A thin film transistor array panel is completed by patterning the passivation layer and the gate insulating layer thereunder using a fourth mask, thereby removing the portion of the passivation layer and the gate insulating layer on the gate pads.
As a result, the gate pads of aluminum or aluminum alloy are exposed in the conventional manufacturing method of photolithography using four masks. However, aluminum and aluminum alloy is vulnerable to the external physical and chemical stimuli and get easily damaged, even though they have advantages of a low resistivity. To compensate this matter, the gate lines are formed having a multiple-layered structure or made of materials that can endure physical and chemical stimuli. However, the former method complicates the manufacturing process, and the latter has a problem of a high resistivity.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide new methods for manufacturing a thin film transistor array panel for a liquid crystal display with a reduced number of masks.
It is another object of the present invention to protect the gate pads of the liquid crystal displays.
These and other objects are provided, according to the present invention, by forming a thinner portion of a photoresist (PR) layer than other portion between a source electrode and a drain electrode before the two electrodes are formed. Thus, the thin portion of the PR layer protects the underlying layers when some layers are etched, and is also etched along with other layers to expose its underlying layer.
According to the present invention, a gate wire including a gate line, and gate electrodes connected to the gate line, a gate insulating layer covering the gate wire, a semiconductor pattern, and an ohmic contact layer are sequentially formed on an insulating substrate. A data wire including a source electrode and a drain electrode formed of the same layer and separated from each other and a data line connected to the source electrode are formed thereover. A passivation layer pattern that covers the data wire but exposes the drain electrode at least in part is formed, and a pixel electrode connected to the drain electrode is formed. A photolithography process using a photoresist layer having three portions separates the source electrode from the drain electrode. The first portion is located between the source electrode and the drain electrode and has a first thickness, the second portion has a second thickness layer that is greater than the first thickness, and the third portion has no photoresist layer.
The photomask used in this step has three parts and is aligned as follows: the first part partially transmitting light faces the first portion of the photoresist layer; the second part that is substantially opaque faces the second portion; and the third part that is substantially transparent faces the third portion.
At this time, the first part of photomask may have a partly transparent layer or a pattern having at least an opaque portion of a size smaller than the resolution of the light source used in the exposing step.
In another way, the first part of photoresist layer may be formed by reflow of the photoresist layer.
It is preferable that the first portion of the photoresist layer has a thickness equal to or less than a half of that of the second part. In particular, it is preferable that the thickness of the second part is 1 &mgr;m~2 &mgr;m and the thickness of the first part is less than 4,000 Å.
Furthermore, the mask may comprise a fourth part having at least an opaque portion of a size that is smaller than the resolution of the light source used in the exposing step between the first part and the third part.
According to an embodiment of the present invention, a data wire, an ohmic contact layer pattern and a semiconductor pattern can be formed by one mask. A gate insulating layer, the semiconductor pattern, the ohmic contact layer pattern, and the data wire are formed through following steps. At first, a gate insulating layer, a semiconductor layer, an ohmic contact layer, and a conductive layer are deposited, and a photoresist layer is coated thereon. Then, the photoresist layer is exposed to light through a photomask, and developed to form a photoresist pattern. The above-described second portion of the photoresist pattern is located over a data wire. Next, a data wire of the conductive layer, an ohmic contact layer pattern, and a semiconductor pattern are formed by etching the portion of the conductive layer, the ohmic contact layer, and semiconductor layer under the third portion, the first portion, the portion of the conductive layer and underlying ohmic contact layer, and an upper part of the second portion. Thereafter, the photoresist pattern is removed. At this time, the data wire, the ohmic contact layer pattern, and the semiconductor pattern may be formed through three steps. At first, the portion of conductive layer under the third portion is wet or dry etched to expose the ohmic contact layer. Then, the portion of the ohmic contact layer and the semiconductor layer under the third portion are subject to dry etching together with the first part. Thereby, the portion of the gate insulating layer under the third part and the portion of the conductive layer under the first part are exposed, and a complete semiconductor pattern is obtained at the same time. Finally, the data wire and the ohmic contact layer pattern are completed by etching the portion of the conductive layer under the first part and the ohmic contact layer thereunder.
Here, if the data wire is dry etched, the ohmic contact layer pattern and the semiconductor pattern may be completed through one step by adjusting the thickness of the first portion of the photoresist pattern and the dry etch condition.
At this time, the portion between the source electrode and the drain electrode may have one sh
Howrey Simon Arnold & White
Samsung Electronics Co,. Ltd.
Smith Matthew
Yevsikov V.
LandOfFree
Thin film transistor array panel and a method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thin film transistor array panel and a method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thin film transistor array panel and a method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2526714