Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2002-12-09
2004-10-19
Parker, Kenneth (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
Reexamination Certificate
active
06806937
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to thin film transistor (TFT) panel for a liquid crystal display (LCD) and a method for manufacturing the same.
(b) Description of the Related Art
An LCD is one of the most popular flat panel displays (FPD). The LCD has two panels having two kinds of electrodes for generating electric fields and a liquid crystal layer interposed there between. The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
The field-generating electrodes may be formed at each of the panels, or at only one of the panels. A panel with at least one kind of electrode has switching elements, such as thin film transistors.
In general, a TFT array panel of an LCD includes a plurality of pixel electrodes and TFTs controlling the signals supplied to the pixel electrodes. The TFT array panel is manufactured by photolithography using a plurality of photomasks, and it undergoes five or six photolithography steps before it is completed. The high costs and lengthy time required for the photolithography process makes it desirable to reduce the number of the photolithography steps.
Several manufacturing methods of LCDs using only four photolithography steps have been suggested, such as that in Korean Patent Application No. 1995-189 ('189). However, as an LCD actually requires wires for transmitting electric signals to the TFTs and wire pads for receiving external signals, the full process to complete a TFT array panel requires the step of forming such pads. Unfortunately, '189 does not disclose how to form such pads.
Another conventional method of manufacturing a TFT array panel using only four photolithography steps is disclosed in “A TFT Manufactured by 4 Masks Process with New Photolithography (Chang-wook Han et al., Proceedings of The 18th International Display Research Conference Asia Display 98, pp. 1109-1112, 1998. 9.28-10.1).
Furthermore, a storage capacitor for sustaining the voltage applied to a pixel is generally provided in the TFT array panel, and the storage capacitor includes a storage electrode and a portion of a pixel electrode as well as a passivation layer interposed there between. The storage electrode is made of the same layer as a gate wire, and a portion of the pixel electrode is formed on the passivation layer. The storage electrode is covered with a gate insulating layer, a semiconductor layer, and a passivation layer, with most of the pixel electrode being formed directly on the substrate in Han et al. Therefore, the pixel electrode should be stepped up over the triple layers of the gate insulating layer, the semiconductor layer, and the passivation layer in order to overlap the storage electrode. This may result in a disconnection of the pixel electrode in the vicinity of a high step-up area.
As shown in '189, conventional photolithography processes uses a photoresist (PR) layer. The conventional photoresist layer is exposed to light through a photomask and thereby divided into two sections, that is, the part exposed to the light and the other part that is not so exposed. The development of the photoresist layer forms the PR pattern having a uniform thickness once the PR layer exposed to the light has been completely removed. Accordingly, the etched thickness of the layers under the PR pattern is also uniform. However, Han et al. uses a photomask having a grid, which lowers the amount of light reaching the portion of a positive PR layer thereunder in order to form a PR pattern having some portions thinner than other portions. The different thicknesses of the PR pattern produces the different etching depths of the underlying layers.
However, the method of Han et al. has a problem in forming the grid throughout a wide region. Furthermore, it is hard to make the etching depth uniform under the grid region, even when the grid is formed throughout a wide region.
U.S. Pat. Nos. 4,231,811, 5,618,643, and 4,415,262 and Japanese patent publication No. 61-181130, etc., which disclose similar methods as do Han et al. also have the same problem.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to simplify the manufacturing method of a TFT array panel for an LCD, thereby reducing the manufacturing cost and increasing the productivity.
It is another object of the present invention to etch thin films to different uniform depths depending on position at the same time.
These and other objects are provided, according to the present invention, by forming a contact hole for a gate pad along with at least one other layer, or a data wire and a semiconductor pattern, using a photoresist pattern as the etch mask, which is formed by a single photolithography step, having different thickness depending on position.
At this time, the semiconductor pattern may be extended out from the data wire.
In the manufacturing method of a thin film transistor array panel for a liquid crystal display of the present invention, a gate wire including a plurality of gate lines, gate electrodes, and gate pads, and a common wire including common signal line and common electrodes, are formed on a substrate having a display area and a peripheral area. The gate lines, and the gate electrodes and the common wire are mainly located in the display area and the gate pads are mainly located in the peripheral area. A gate insulating layer pattern covering portions of the gate wire and the substrate in the display area and exposing at least a part of each gate pad is formed thereon. A semiconductor pattern is formed on the gate insulating layer pattern, and an ohmic contact layer pattern is formed on the semiconductor pattern. Then, a data wire including a plurality of data lines, source electrodes, and drain electrodes mainly located in the display area and a plurality of data pads mainly located in the peripheral area are formed on the ohmic contact layer pattern. Next, a passivation layer pattern is formed, and a pixel wire including a plurality of pixel electrodes and pixel signal lines and which are connected to the drain electrodes is formed. Here, the gate insulating layer pattern is formed along with the semiconductor pattern and the passivation layer pattern through a single photolithography process using a photoresist pattern having a thickness that varies depending on position.
Here, it is desirable that the photoresist pattern has a first portion located over the gate pads, a second portion that is thicker than the first portion and located in the display area, and a third portion that is thicker than the second portion.
The photoresist pattern is formed on the passivation layer. The gate insulating layer pattern, the semiconductor layer pattern, and the passivation layer pattern are formed by etching a passivation layer and a semiconductor layer under the first portion of the photoresist pattern, and the second portion of the photoresist pattern at the same time. Next, the second portion of the photoresist pattern, in order to expose the passivation layer thereunder, is removed by an ashing process, and the gate insulating layer and the passivation layer are etched by using the photoresist pattern as an etch mask to expose the gate pads under the first portion of the photoresist pattern and to expose the semiconductor layer under the second portion of the photoresist pattern. Next, a portion of the semiconductor layer under the second portion is removed by using the photoresist pattern as an etch mask.
The data pads may be exposed in the step of etching the portions of the passivation layer and the semiconductor layer, and the data pads are exposed in the step of etching the passivation layer and the gate insulating layer.
The drain electrodes may be exposed in the step of etching the passivation layer, or they may be exposed in the step of etching portions of the passivation layer and the semiconductor layer.
A plurality of redundant gate pads and redundant data pads respectively covering the gate pad and the data pad may be formed in the
Park Woon-Yong
Yoon Jong-Soo
McGuireWoods LLP
Parker Kenneth
Samsung Electronics Co,. Ltd.
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