Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2003-08-21
2004-09-07
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S059000
Reexamination Certificate
active
06787809
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a thin film transistor array panel for a liquid crystal display and a method for manufacturing the same, especially to a method for manufacturing a thin film transistor array panel with a reduced number of photolithography steps.
(b) Description of the Related Art
A liquid crystal display (LCD) is one of the most popular FPDs (flat panel displays). The LCD has two panels having electrodes for generating electric fields and a liquid crystal layer interposed therebetween. The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
In the most widely used LCD, the field-generating electrodes are provided at both panels, and one of the panels has switching elements such as thin film transistors (TFTs).
In general, a thin film transistor array panel is manufactured by photolithography using a plurality of photomasks, and five or six photolithography steps are used. The high cost for the photolithography process makes it desirable to reduce the number of the photolithography steps. Even though a few manufacturing methods using only four photolithography steps are suggested, these methods are not easy to accomplish.
Now, a conventional method of manufacturing a thin film transistor array panel using four lithography steps will be described.
First, a gate wire of aluminum or aluminum alloy are formed on a substrate by using a first mask. A gate insulating layer, an amorphous silicon layer, an n+ amorphous silicon layer and a metal layer are sequentially deposited. The metal layer, the n+ amorphous silicon and the amorphous silicon layer are patterned by using a second mask. At this time, gate pads of the gate wire is covered only with the gate insulating layer. An ITO (indium tin oxide) layer is deposited and patterned by using a third mask. At this time, the portions of the ITO layer over the gate pads are removed. After the metal layer and the n+ amorphous silicon layer thereunder are patterned by using the patterned ITO layer as an etch mask, a passivation layer is deposited. A complete thin film transistor array panel is obtained by patterning the passivation layer and gate insulating layer thereunder using a fourth mask, thereby removing the portion of the passivation layer and the gate insulating layer on the gate pads.
As a result, the gate pads of aluminum or aluminum alloy are exposed in the conventional manufacturing method of using four masks. The aluminum and the aluminum alloy cannot stand against physical and chemical variations and are vulnerable to damage and oxidation, despite their advantages of low resistivity. To compensate this matter, gate lines are formed to have multiple-layered structure or made of materials that can stand against the physical and chemical changes. However, the former makes the manufacturing process complicated, and the latter may result in a high resistivity problem.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide new methods for manufacturing a thin film transistor array panel for LCDs with a reduced number of photolithography steps.
It is another object of the present invention to protect gate pads of LCDs.
It is the other object of the present invention to prevent the LCD's current leakage.
These and other objects are achieved, according to the present invention, by patterning the gate insulating layer, the semiconductor layer, the ohmic contact layer and the data conductor layer at a time.
According to the present invention, a gate wire is formed on an insulating substrate by a first photolithography process. A quadruple layers including a gate insulating layer, a semiconductor layer, an ohmic contact layer and a data conductor layer is deposited on the insulating substrate and the gate wire and formed by a second photolithography process. A conductive pattern is formed on the data conductor layer and the area surrounded by the data conductor layer by a third photolithography process. Then, the portion of the data conductor layer not covered by the conductive pattern is etched out to form a data wire and the ohmic contact layer not covered by the data wire is also etched out. Finally, a passivation layer pattern on the conductive pattern is formed by a fourth photolithography process.
At this time, the gate wire may include a plurality of gate lines extended to a first direction, gate electrodes that are branches of the gate line and gate pads connected to an end of the gate line and receiving a scanning signal from an external circuit. The quadruple layers may have first contact holes exposing the gate pad, and the passivation layer may have second contact holes exposing the first contact hole.
The gate wire may include a plurality of gate lines extended to a first direction, gate electrodes that are branches of the gate line and gate pads connected to an end of the gate line and receiving a scanning signal from an external circuit. The quadruple layers may have first contact holes exposing the gate pad. The conductive pattern may include first conductive patterns connected to the gate pad through the first contact hole, and the passivation layer may have second contact holes exposing the first conductive pattern.
The gate wire may include a plurality of gate lines extended to a first direction, gate electrodes that are branches of the gate line and gate pads connected to an end of the gate line and receiving a scanning signal from an external circuit. The data wire may include a plurality of data lines extended to a second direction and crossing the gate line, data pads connected to an end of the data line and receiving an image signal from an external circuit, source electrodes connected to the data line and adjacent with the gate electrode, and drain electrodes located at the opposite side of the source electrode with respect to the gate electrode. The conductive pattern may include a plurality of first conductive patterns formed on the data line, the source electrode and the data pad, second conductive patterns formed on the drain electrode, and pixel electrodes connected to the second conductive pattern and formed in the area surrounded by the gate line and the data line. The passivation layer may have first openings exposing the pixel electrode and second openings exposing the first conductive pattern on the data pad. The passivation layer may have third openings exposing a part of the semiconductor layer between the adjacent two data line. The step may further comprise a step of etching the exposed portion of the semiconductor layer to separate the semiconductor layer under the two data line from each other. The pixel electrode may be overlapped with the previous gate line and the portion of the semiconductor layer sandwiched between the pixel electrode and the gate line is isolated from the other portion.
The gate insulating layer may include a first portion formed between the gate pads and between the data pads, the passivation layer may have a fourth opening exposing the first portion of the gate insulating layer. The portion of the semiconductor layer located on the first portion of the gate insulating layer may be removed to separate the portions of the semiconductor layer under the gate pads and the data pads.
The passivation layer may cover the edge of the pixel electrode. The first opening exposes the edge of the pixel electrode. A storage wire overlapped with the pixel electrode may be formed on the substrate, the quadruple layers may be formed on the storage wire, and the portion of the semiconductor layer sandwiched between the storage wire and the pixel electrode is isolated from the other portion.
The passivation layer may have a trench exposing the portion of the semiconductor layer between the first conductive pattern and the pixel electrode and between the adjacent pixel electrodes, and further comprising a step of etching the exposed semiconductor layer through the trench. The gate line may include two m
Hong Mun-Pyo
Park Woon-Yong
Yoon Jong-Soo
McGuireWoods LLP
Prenty Mark V.
Samsung Electronics Co,. Ltd.
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