Thin film transistor array panel

Details Thin film transistor array panel Thin film transistor array panel

2007-10-02

2007-10-02

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

C257S072000, C257SE21113, C257SE21111

Reexamination Certificate

active

11234470

ABSTRACT:
A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.

REFERENCES:
patent: 2004/0222421 (2004-11-01), Lee et al.
patent: 2004/0263706 (2004-12-01), Cho et al.

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