Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2003-04-01
2004-06-15
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S586000, C438S945000
Reexamination Certificate
active
06750087
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor array substrate and fabrication method thereof, and relates to a thin film transistor substrate employed in a liquid crystal display device, for example.
2. Related Background Art
The application of electrical optical elements employing liquid crystals to displays has been the subject of active research. Of these elements, TFT-LCDs which employ thin film transistors (referred to below as TFTs) as switching elements are superior in terms of portability, low electrical power consumption and display quality, and are therefore widely used. In order to attain more widespread usage, further cost reductions are required. As one measure for achieving further cost reductions, the reduction of the number of TFT array fabrication steps for increased productivity has been investigated.
An attempt to eliminate photolithography processes, that is, masks, is illustrated in Japanese Patent Laid-open application No. 2000-111958. A cross-sectional view of a pixel section of a TFT array substrate fabricated by four photolithography processes is shown in
FIG. 2A
, and the description will be provided using this cross-sectional view.
In this prior art example, after an electrically conductive film with a thickness on the order of 100 nm has been deposited on a transparent substrate, a resist pattern is formed using a first mask in a first photolithography process and gate line
1
is then formed by etching. Next, a gate insulation film
3
, a semiconductor layer
4
a
, and an ohmic layer
4
b
(described as a ‘contact layer’ in Japanese Patent Laid-open application No. 2000-111958) are deposited on the transparent substrate on which the gate line
1
is formed so as to have the respective thicknesses 150 to 500 nm, 50 to 150 nm, and 30 to 60 nm. A metal film
16
is then deposited in a thickness of 150 to 300 nm.
In a second photolithography process, a second mask is used to form a resist pattern
17
(described as a ‘photosensitive film’ in Japanese Patent Laid-open application No. 2000-111958) thickly on a source electrode
5
, source line
6
(described as ‘data wire’ in Japanese Patent Laid-open application No. 2000-111958), and a drain electrode
7
, and thinly in the corresponding section to a semiconductor active layer
8
(described as a ‘channel section’ in Japanese Patent Laid-open application No. 2000-111958). The thick resist pattern on the source electrode
5
, source line
6
, and drain electrode
7
will be referred to below as the ‘normal film thickness resist pattern
17
a
, and the thin resist pattern in the corresponding section to the semiconductor active layer
8
will be referred to below as the thin film resist pattern
17
b
. The metal film is then removed by wet etching or similar. Thereafter, the thin film resist pattern
17
b
, the ohmic layer
4
b
, and the semiconductor layer
4
a
which lies beneath the ohmic layer
4
b
are removed at the same time by dry etching. As a result of this processing, the metal film
16
is exposed in the corresponding section to the semiconductor active layer
8
. Then, the metal film
16
in the corresponding section to the semiconductor active layer
8
is removed by wet etching to expose the ohmic layer
4
b
beneath the metal film
16
. In addition, part of the semiconductor layer
4
a
and of the ohmic layer
4
b
of the corresponding section to the semiconductor active layer
8
are removed by dry etching, whereupon the resist is stripped away. Then SiNx, which constitutes an intermediate insulation film
9
, is stacked with a thickness of 300 nm or more. In a third photolithography process, patterning is carried out using a third mask, and the intermediate insulation film
9
, and the gate insulation film are then etched. An electrically conductive layer of 40 to 50 nm is also stacked. Ultimately, in a fourth photolithography process, patterning is carried out using a fourth mask and the electrically conductive film is etched, thereby completing the TFT. In the above fabrication method, a reduction of the number of masks is achieved by varying the thickness of the resist of the second mask according to location.
In the fabrication process for a TFT array substrate formed according to the prior art which is shown in
FIGS. 16A
to
16
E, the details of the steps in the second photolithography process are shown. In the prior art illustrated by Japanese Patent Laid-open application No. 2000-111958, the thin film resist pattern
17
b
, the ohmic layer
4
b
, and the semiconductor layer
4
a
which lies beneath the ohmic layer
4
b
are removed at the same time by dry etching. Further, in the prior art shown in Japanese Patent Laid-open application No. 2001-339072, after the ohmic layer
4
b
and the semiconductor layer
4
a
are removed by dry etching, the thin film resist pattern
17
b
is removed by ashing.
FIG. 16A
shows a structure of a TFT array substrate that pertains to a stage in which a resist pattern
17
which comprises the thick normal film thickness resist pattern
17
a
on the source electrode
5
, the source line
6
, and the drain electrode
7
and the thin film thickness resist pattern
17
b
in the corresponding section to the semiconductor active layer
8
is formed, and the metal film
16
is then removed by wet etching or similar. Here, the structure is such that the metal film
16
lies inwards from the ends of the resist pattern
17
as a result of side etching.
FIG. 16B
shows a structure of the TFT array substrate that pertains to a stage in which the ohmic layer
4
b
and the semiconductor layer
4
a
are removed by dry etching, which constitutes the next step.
FIG. 16C
shows a structure of the TFT array substrate that pertains to a stage in which the thin film resist pattern is removed by ashing, which constitutes the next step.
FIG. 16D
shows a structure of the TFT array substrate that pertains to a stage in which the metal film
16
in the corresponding section to the semiconductor active layer
8
is removed to expose the ohmic layer
4
b
beneath the metal film.
FIG. 16E
shows a structure of the TFT array substrate that pertains to a stage in which part of the semiconductor layer
4
a
and of the ohmic layer
4
b
of the corresponding section to the semiconductor active layer
8
is removed by dry etching before the resist is stripped away. At this stage, the source electrode
5
, the drain electrode
7
, and the semiconductor active layer
8
are exposed.
In the eighth embodiment example of the above-described Japanese Patent application Laid-open No. 2000-111958, following the formation of the resist pattern in the second photolithography process, etching of the metal film is carried out and then the thin resist, the ohmic layer and the semiconductor layer above the channel are removed at the same time. Further, according to Japanese Patent application Laid-open No. 2001-339072, after the ohmic layer and the semiconductor layer are removed by etching, the thin film resist pattern is removed by ashing. The following problems arise with such conventional technology.
Because the photosensitive material of the resist used by the second mask is viscous and fluid, the ends of the resist pattern are shaped with a taper angle. In cases where baking is performed in order to increase the bond strength between the metal film and the resist before the metal film is etched, this inclination becomes prominent. Hence, when the thin resist above the channel is removed, because sections of the thick resist are also tapered in other locations, the ends of the resist pattern are retracted to reduce the surface area of the resist pattern. The smaller the taper angle of the resist pattern, the greater the degree of this retraction.
On the other hand, because the semiconductor layer is removed prior to or at the same time as the removal of the thin film resist pattern, this layer is barely influenced by the area of the resist pattern, that is, by the taper angle of the same. Hence, following the removal of
Morita Hiromasa
Nakashima Ken
Advanced Display Inc.
Chaudhari Chandra
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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