Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Non-single crystal – or recrystallized – material with...
Reexamination Certificate
2001-11-20
2004-11-09
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Non-single crystal, or recrystallized, material with...
C257S065000, C257S070000, C257S075000, C257S347000
Reexamination Certificate
active
06815717
ABSTRACT:
This application is based on Japanese Patent Application No. 2001-042694 filed in Japan, the contents of which are incorporated hereinto by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a thin-film transistor used in liquid-crystal display devices and a process of manufacturing the thin-film transistor.
2. Description of the Related Art
In recent years, in liquid-crystal display used as display devices such as notebook personal computers, mobile appliances and so forth, their drive systems are being changed over from simple matrix systems to active matrix systems. In particular, thin-film transistor (hereinafter often “TFT”) active matrix drive systems are becoming prevailing in which a large number of thin-film transistors have been formed on a glass substrate.
Among TFT drive systems, TFTs making use of polycrystalline silicon layers have a larger electron mobility than those making use of amorphous silicon layers. Hence, they can be fabricated on glass substrates not only as transistors of displaying pixel areas but also as driving transistors.
Conventionally, since the formation of polycrystalline silicon requires a high temperature of about 1,000° C., it has been indispensable to use expensive quartz glass substrates as substrates.
Recently, development has been brought forward on techniques by which polycrystalline silicon can be formed at a processing temperature of about 600° C., and it has become possible to use glass materials other than quartz substrates. In this method, amorphous silicon film formed on a glass substrate is subjected to laser irradiation or the like, whereby only the amorphous silicon film can be heated and crystallized without causing a rise in substrate temperature.
Meanwhile, in integrated circuit devices making use of single-crystal silicon substrates, thermal oxides (layer thickness: about few nm to tens of nm) of silicon are used as gate-insulating layers. However, the formation of such thermal oxides of silicon requires heat treatment at about 1,000° C., and this processing can not be utilized in the process of manufacturing polycrystalline silicon TFTs which prerequisites the processing temperature of 600° C. or below.
In processes of manufacturing TFTs, TEOS (tetraethoxysilane) is used as a material, and SiO
2
layer (layer thickness: about 100 nm) formed by plasma-assisted CVD (chemical vapor deposition) is used as gate-insulating layer. The SiO
2
layer formed by plasma-assisted CVD (hereinafter “TEOS layer”), however, has so high an interfacial state density that a great performance deterioration of TFT characteristics may be brought about as is seen in, e.g., variations of threshold voltage when it is used as the gate-insulating layer as it is. Moreover, in such a case, the breakdown strength of TFT may severely deteriorate with time to cause dielectric breakdown of the TFT as a result thereof. Accordingly, at the interface of the gate-insulating layer for TFT and the silicon layer, it is desirable to form an oxide layer having low interfacial state density, comparable to thermal oxides formed by thermal oxidation of silicon.
To cope with the above problem, e.g., Japanese Patent Application Laid-open No. 8-195494 discloses a method of manufacturing a polycrystalline silicon TFT at a processing temperature of 600° C. or below, using a conventional highly heat-resistant glass substrate.
According to the above method disclosed in Japanese Patent Application Laid-open No. 8-195494, since the polycrystalline silicon layer is formed at a temperature of about 600° C., a usable glass substrate is limited to an annealed glass substrate. Hence, when an unannealed glass substrate is used in place of the annealed glass substrate, the temperature condition of about 600° C. may cause a shrinkage of the glass substrate, and this may cause a warpage or strain of the glass substrate to bring about difficulties such as break of the glass substrate itself and peel of the layer, at worst.
In general, the higher strain point the glass has, the higher thermal stability it has. Such glass, however, is difficult to melt, mold and work in the step of producing the glass substrate, resulting in a high production cost. Accordingly, in order to control the cost, a production method is essential which enables use of glass which has a low strain point and is inexpensive.
Usually, alkali-free glass substrates used as substrates of thin-film transistors have a strain point of about 600° C., and compaction (heat shrinkage) of glass becomes great abruptly as a result of heat history at upper temperatures than at a temperature a little lower than the strain point. For example, an unannealed glass substrate CORNING 7059F (Trade name: available from Corning Glass works; strain point 593° C.) shows a compaction of about 800 ppm as a result of heat history at 600° C., for 1 hour and at a cooling rate of 1° C./minute. Also, in the case of CORNING 1735F (strain point: 665° C.), having a higher strain point, it shows a compaction of 173 ppm upon application of the same heat history as the above. Then, it has been made possible to lower compaction due to the like heat history to about 10 ppm by carrying out annealing previously at 660° C./1 hr.
Substrates for polycrystalline TFT panels are usually required to show a heat shrinkage rate (compaction) of 20 ppm or less. Accordingly, it has ever been considered indispensable to use annealed glass substrates (Liquid-Crystal Display Fabrication Technique Handbook, compiled by Ryuji Shimada, published by Science Forum, pp.191-199). Thus, where the upper limit of processing temperature is merely lowered to temperature of such a degree that the shrinkage of unannealed glass substrates is negligible, e.g., to 450-500° C., a problem discussed below may occur.
That is, as a gate-insulating layer formed on a polycrystalline silicon layer, as stated previously an SiO
2
layer is formed in a layer thickness of about 100 nm by plasma-assisted CVD (chemical vapor deposition) using TEOS (tetraethoxysilane) as a material gas (herein “TEOS layer”). At the interface between the polycrystalline silicon layer and the insulating layer formed of TEOS, however, the interfacial density of the TEOS layer becomes so high that the threshold voltage required of a TFT tends to vary and also the breakdown strength of the gate-insulating layer thereof may severely deteriorate with time. Thus, there is a great problem on the reliability of TFT.
SUMMARY OF THE INVENTION
Hence, in the case when the use of an unannealed glass substrate is premised, it is important to design to keep the upper limit of processing temperature at about 450 to 500° C. and lower the interfacial state density between the polycrystalline silicon layer and the gate-insulating layer to a level corresponding to that of any silicon oxide layer formed by thermal oxidation.
An object of the present invention is to solve the problem discussed above, and form a highly reliable TFT having a polycrystalline silicon layer, under low-temperature processing conditions and yet on an unannealed glass substrate. Here, in the present invention, a glass substrate showing a compaction of 30 ppm or higher when the glass substrate is heated at 600° C. for 1 hour and thereafter cooled at a rate of 1° C./minute is defined as the unannealed glass substrate.
To achieve the above object, in the present invention, i) a polysilicon crystal layer for forming a channel region, a source region and a drain region and ii) a first insulating layer and a second insulating layer are formed at the upper part of an unannealed glass substrate. Also, a gate region is formed at a position corresponding to the channel region and on the second insulating layer. And a gate electrode, a source electrode and a drain electrode are also formed to make electrical interconnection with the gate region, the source region and the drain region, respectively.
Here, it is preferable that the first insulating layer is a silicon oxide layer formed by oxidizing the surface of the channel region at a tem
Horikoshi Kazuhiko
Itoga Toshihiko
Kamo Takahiro
Nakahara Miwako
Nakano Yasushi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Tran Thien F
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