Thin film transistor and method of forming thin film transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

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438142, 438149, H01L 2100

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active

060177829

ABSTRACT:
A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

REFERENCES:
patent: 4385937 (1983-05-01), Ohmura
patent: 4420870 (1983-12-01), Kimura
patent: 4498224 (1985-02-01), Maeguchi
patent: 4528480 (1985-07-01), Unagami et al.
patent: 5112764 (1992-05-01), Mitra et al.
patent: 5198379 (1993-03-01), Adan
patent: 5208476 (1993-05-01), Inoue
patent: 5266507 (1993-11-01), Wu
patent: 5286663 (1994-02-01), Manning
patent: 5292675 (1994-03-01), Codama
patent: 5308998 (1994-05-01), Yamazaki et al.
patent: 5323042 (1994-06-01), Matsumoto
patent: 5344790 (1994-09-01), Bryant et al.
patent: 5412493 (1995-05-01), Kunii et al.
patent: 5420055 (1995-05-01), Vu et al.
patent: 5457058 (1995-10-01), Yonehara
Webster's Ninth New College Dictionary, p. 1198, 1990.
Wolf, S., "Silicon Processing For The VLSI Era", vol. II, pp. 354-361 and 436-439.
Hayden et al., A High-Performance Quadruple Well, Quadruple Poly BiCMOS Process For Fast 16Mb SRAMs, IEEE, IEDM 92/819, pp. 819-822, 1992.
Tanaka et. al., "Field-Induction Drain (FID) Poly-Si TFTs With High On/Off Current Ratio", Extended Abstracts of the 22nd Conf. on S.S. Devices and Materials, 1990, pp. 1011, 1014.
Hashimoto et. al., "Thin Film Effects of Double-Gate Polysilicon MOSFET", Ext. Abstract of the 22nd Conf. of S.S. Devices and Materials, 1990, pp. 393-396.
Batra et. al., "Development of Polysilicon TFTs for 16Mb SRAMs and Beyond", Sep. 28, 1994, 2 pages.
Batra, Shubneesh, Development of Drain-Offset (DO) TFT Technology for High Density SRAMs, Oct. 9, 1994, 2 pages.
Jung et. al., "A Leakage Current Model for Sub-Micron Drain-Offset Polysilicon TFTs", Oct. 9, 1994, 4 pages.
Colinge et. al., "Field Effect in Large Grain Polycrystalline Silicon", IEEE Transactions on Electron Devices, vol. ED-30, No. 3, Mar. 1983, pp. 197-201.
Hasimoto et al., This Film Effects of Double-Gate Polysilicon MOSFET, Ext. Abstracts of the 22nd Conf. of S.S. Devices and Materials, 1990, pp. 393-396.
Batra et al., "Development of Polysilicon TFT's for 16 Mb SRAMs and Beyond", SB Sep. 28, 1994, Jun. 21, 1993.
Batra, Shubneesh, "Development of Drain-Offset (DO) TFT Technology for High Density SRAMs", Oct. 9, 1994.

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