Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-08-09
2004-06-08
Wilson, Allan R. (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S216000, C438S287000, C438S591000
Reexamination Certificate
active
06746905
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the structure of a thin film transistor used as, e.g., the switching element of a liquid crystal display, and a manufacturing process therefor, and relates to a thin film transistor array using a thin film transistor with the above structure, and the structure of an active matrix liquid crystal display.
An active matrix liquid crystal display using a twisted nematic (TN) liquid crystal has excellent characteristics such as a large capacity and a high density, and is widely used for a television image display, a graphic display, and the like.
To provide a high-contrast display free from any crosstalk, such an active matrix liquid crystal display employs a scheme of driving and controlling each pixel by using a semiconductor switching element. The semiconductor switching element for this application is often a thin film transistor (TFT) in which a semiconductor active layer (channel, source, and drain regions) is formed of amorphous silicon (a-Si) on a glass substrate because it is capable of transmission type display and its area can be relatively easily increased.
Generally known structures of such amorphous silicon TFTs are an inverted staggered TFT in which the gate electrode is arranged below the amorphous silicon layer serving as an active layer, a staggered TFT in which the gate electrode is arranged above the amorphous silicon layer.
Of these structures, the inverted staggered TFT has good transistor characteristics. However, since the gate electrode is arranged underneath the amorphous silicon layer, the resistance of the gate electrode wiring line (scanning line) is difficult to decrease. When a TFT is applied to an active matrix liquid crystal display, of the constituent elements of the TFT, the gate electrode wiring line needs to have low resistance. This problem becomes more serious when the LCD is large in size. As for the productivity, 6 or more photomasks are normally required for the inverted staggered structure, so a cost reduction is difficult to attain.
In the staggered TFT, the gate electrode is arranged above the amorphous silicon layer (top gate type), and the source and drain electrodes are arranged below the amorphous silicon layer. The staggered TFT is advantageous in terms of the productivity and the manufacturing cost because the number of photomasks can be minimized to 2. In addition, since the staggered TFT is of the top gate type, Al can be used as the material of the gate electrode wiring line and it is easy to form a thick film.
However, this conventional staggered structure also has the following problems. First, it is difficult to obtain an ohmic contact between n
+
a-Si formed on the source and drain electrodes and a-Si of the active layer, therefore a sufficient ON current cannot be ensured for the TFT. Although it has been proposed to use ITO (Indium Tin Oxide) for the source and drain electrodes and to process the ITO surface with a PH
3
plasma before formation of a-Si, the a-Si layer formed subsequently is adversely affected due to contamination with P. In addition, since the source and drain electrodes overlap the gate electrode, the parasitic capacitances between the gate and source and between the gate and drain increase.
U.S. Pat. No. 4,727,044 discloses the following process for manufacturing a top gate TFT. That is, an amorphous silicon layer is formed on a glass substrate, and a gate electrode is formed on this amorphous silicon layer via a gate dielectric layer. Using this gate electrode as a mask, ion doping and laser irradiation are performed for the amorphous silicon layer at portions corresponding to source and drain regions to crystallize the amorphous silicon layer in the regions. The amorphous silicon layer at a portion masked by the gate electrode constitutes a channel. When this process is used to manufacture a coplanar type TFT which is one of top gate TFTs and employed in a monocrystalline silicon LSI, the following process is further performed. The gate electrode and the source and drain regions are covered with an insulating protective layer, a contact hole is formed in this insulating protective layer, and source and drain electrodes are formed.
However, the above TFT structure disclosed in U.S. Pat. No. 4,727,044 has the following problems.
In an application to a liquid crystal display, the amorphous silicon layer must be processed into an island shape, and the semiconductor layer must be isolated between adjacent TFTs. In this case, the amorphous silicon layer is processed into an island shape before formation of a gate dielectric layer. However, a clean interface (channel interface) between the amorphous silicon layer and the gate dielectric layer is difficult to provide, so a TFT having high mobility and high reliability cannot be obtained.
In doping ions into the amorphous silicon layer corresponding to the source and drain regions, a very large acceleration voltage is required because the ions are doped through the gate dielectric layer into the underlying amorphous silicon layer. In the process for manufacturing a monocrystalline silicon LSI, ions are normally doped through a gate dielectric layer. Ion doping through the gate dielectric layer is possible because the thickness of the gate dielectric layer is as thin as 50 nm or less. To the contrary, in a TFT used for a liquid crystal display, a gate dielectric layer generally also serves as an interlevel insulating layer between scanning and signal lines in order to decrease the number of steps. To ensure the insulation properties, or to reduce the capacitance at the cross portion between the scanning and signal lines, the thickness of the gate dielectric layer is set to about 200 to 500 nm. With such a thickness, ions cannot reach the amorphous silicon layer even at an ion doping acceleration voltage of 100 kV; in practice, ion doping through the gate dielectric layer is impossible.
In crystallizing the amorphous silicon layer by laser irradiation, if the laser is irradiated through the gate dielectric layer, ablation easily occurs to scatter amorphous silicon along with discharge of a gas, such as hydrogen gas, from the amorphous silicon layer. In addition to ablation, since interference of the laser beam is caused by the dielectric layer on the amorphous silicon layer, the intensity of the laser beam incident on the amorphous silicon layer undesirably changes in correspondence with variations in thickness of the dielectric layer.
As described above, the amorphous silicon layer cannot be stably crystallized by irradiating the laser through the gate dielectric layer.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation, and has as its object to provide a manufacturing process and structure of a thin film transistor having high productivity in which a clean interface can be formed between a channel and a gate dielectric layer, and the resistance of a gate electrode wiring line (scanning line) is easily decreased, a semiconductor active layer and source and drain electrodes reliably form an ohmic contact, and the number of masks required in the manufacturing process can be decreased.
Process for Manufacturing Thin Film Transistor
According to the present invention, there is provided a process for manufacturing a thin film transistor, which comprises the steps of:
depositing an amorphous silicon layer on an insulating substrate;
depositing a 1-st gate dielectric layer consecutively to the step of depositing the amorphous silicon layer;
patterning the amorphous silicon layer together with the 1-st gate dielectric layer into an island shape;
depositing a 2-nd gate dielectric layer to cover the 1-st gate dielectric layer patterned into the island shape;
depositing a conductive layer on the 2-nd gate dielectric layer;
patterning the conductive layer to form a gate electrode; and
doping an impurity ion into the amorphous silicon layer by using the gate electrode as a mask.
According to the thin film transistor manufacturing process of the present
Brock II Paul E
Pillsbury & Winthrop LLP
Wilson Allan R.
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