Thin film transistor and manufacturing method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257348, H01L 2701, H01L 2712, H01L 310392

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active

058215859

ABSTRACT:
A thin film transistor includes an active layer having an offset region formed between a channel region and a drain region, a first insulating film formed on an upper surface of the active layer, a gate electrode formed at a position opposing to the channel region with the first insulating film interposed, and a second insulating film formed at a position opposing to the offset region with the first insulating film interposed and including impurities for forming charges. The charges formed in the second insulating film are provided by implanting fluorine ions, for example, if the charges are to be negative charges. By this structure, the on current of the thin film transistor can be increased and the leak current can be reduced.

REFERENCES:
patent: 4007294 (1977-02-01), Woods et al.
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"Field-Induction-Drain (FID) Poly-Si TFTS with High On/Off Current Ratio", Kengi Tanaka et al., Extended Abstracts of the 22nd (1990 International Conference on Solid State Devices and Materials, Sendai, 1990, pp. 1011-1014.
"A Simple Polysilicon Thin Film Transistor Structure for Achieving High On/Off Current Ratio Independent of Gate Bias", Kanicki and Hatalis, Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials, pp. 52-54.
"Thin Film Transistor", Takeshi Okazawa et al., Nikkei Microdevices 1988 Sep. No. 39, pp. 123-130.
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"16Mbit SRAM Cell Technologies for 2.0V Operation", H. Ohkubo et al., IEDM 1991, pp. 481-484.
"Performance and Reliability Improvement in Poly-Si TFTS by Fluorine Implantation", S. Maegawa et al., IEDM 1993, pp. 41-44.
"Trench-Isolation Technology using A1 Ion Implantation in a SIO2 Layer", Takao Miura et al., 1988 Symposium on VLSI Technology, pp. 19-20.
"Negative Bias Temperature Instability in Poly-Si TFTS's", Maeda et al. 1993 Symposium on VLSI Technology pp. 29-30.

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