Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-08-22
2002-08-13
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S687000
Reexamination Certificate
active
06432755
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to thin film transistors (hereinafter referred to as TFTs) and to manufacturing methods therefor, and more particularly, to a TFT structure in which copper is used as a low resistance material specifically for source and drain wiring.
2. Description of the Related Art
In conventional common TFT liquid crystal display devices, a TFT array substrate having a reverse-stagger type TFT, gate wiring, source wiring, and the like is provided, as shown in
FIG. 6
as a structural example. In the TFT array substrate, as shown in
FIG. 6
, gate wiring
50
and source wiring
51
are disposed in the form of a matrix on a transparent substrate composed of glass or the like. An area surrounded by the gate wiring
50
and the source wiring
51
is a pixel
52
, and a TFT
53
is formed in each pixel
52
. Recently, copper, which is a low resistance material, has attracted attention as a wiring material for use in this kind of liquid crystal display device, semiconductor device, and the like. Accordingly, one example will be described below in which copper is applied to a TFT array substrate.
FIG. 4
is a cross-sectional view of the TFT array substrate, and
FIGS. 5A
to
5
E are cross-sectional views of the TFT showing a manufacturing process therefor.
In the TFT
53
as shown in
FIG. 4
, a gate electrode
55
extending from the gate wiring
50
is formed on a transparent substrate
54
, and a gate insulation film
56
is formed so as to cover the gate electrode
55
. A semiconductor active layer
57
composed of amorphous silicon (a-Si) is formed on the gate insulation film
56
above the gate electrode
55
. A source electrode
59
extending from the source wiring
51
and a drain electrode
60
are formed above ohmic contact layers
58
formed on the semiconductor active layer
57
above the gate insulation film
56
, in which the ohmic contact layers
58
are composed of amorphous silicon (a-Si:n
+
) containing an n-type impurity such as phosphorus. The source wiring
51
, source electrode
59
, and the drain electrode
60
are formed of copper.
When the source electrode
59
and the drain electrode
60
are formed of copper, and when silicon forming the semiconductor active layer
57
and copper are placed directly in contact with each other, a problem arises with regard to copper film separation due to poor cohesion between silicon and copper, or degradation of TFT characteristics due to copper diffusion into silicon. Consequently, metal layers composed of, for example, titanium or molybdenum, are formed under the copper as barrier metal layers
61
so that the source wiring
51
, the source electrode
59
, and the drain electrode
60
have a two-layer structure composed of a barrier metal and copper.
Then, a passivation film
62
is formed so as to cover the TFT
53
composed of the source electrode
59
, the drain electrode
60
, the gate electrode
55
, and the like. A contact hole
63
is formed in the passivation film
62
above the drain electrode
60
. A pixel electrode
64
is further formed, which is composed of a transparent conductive film, such as an indium-tin-oxide compound (hereinafter referred to as ITO), and is electrically connected to the drain electrode
60
via the contact hole
63
.
A left side of the discontinuity in
FIG. 4
shows a cross-sectional structure of a gate terminal pad portion
65
which is an end portion of the gate wiring located outside the display area. As shown in this figure, a contact hole
67
penetrating the gate insulation film
56
and the passivation film
62
is formed above a lower pad layer
66
composed of a gate wiring material on the transparent substrate
54
, and an upper pad layer
68
is formed of the same transparent conductive film as that used for the pixel electrode
64
so as to be electrically connected with the lower pad layer
66
via the contact hole
67
.
When the thin film transistor array substrate is manufactured, as shown in
FIG. 5A
, a conductive film is formed on the transparent substrate
54
, and is then patterned, so that the gate electrode
55
and the gate wiring
50
are formed. In addition, the lower pad layer
66
is formed in the gate terminal pad portion
65
.
Next, as shown in
FIG. 5B
, after forming the gate insulation film
56
so as to cover the gate electrode
55
and the gate wiring
50
, an a-Si film (to later become semiconductor active layer
57
), and an a-Si:n
+
film
69
are sequentially formed, and the a-Si film and the a-Si:n
+
film
69
thus formed are simultaneously patterned by using a photo mask, whereby an island
70
is formed above the gate electrode with the gate insulation film
56
provided therebetween.
As shown in
FIG. 5C
, after sequentially forming the barrier metal film
61
composed of, for example, titanium or molybdenum, and a copper film
71
over the entire surface of the substrate, the copper film
71
and the barrier metal film
61
are patterned so as to form the drain electrode
60
, the source electrode
59
, and the source wiring
51
, and the a-Si:n
+
film above a channel region composed of the a-Si film is removed so as to form the ohmic contact layers
58
composed of the a-Si:n+film.
Next, as shown in
FIG. 5D
, the passivation film
62
is formed over the entire surface of the substrate, and is then patterned so as to form openings therein above the drain electrode
60
and the lower pad layer
66
, whereby the contact holes
63
and
67
are formed for electrical connections between the drain electrode
60
and the pixel electrode
64
and between the lower pad layer
66
and the upper pad layer
68
, respectively.
Finally, as shown in
FIG. 5E
, the ITO film is formed over the entire surface of the substrate, and is then patterned so as to form the pixel electrode
64
and the upper pad layer
68
. By executing the steps described above, the conventional TFT array substrate shown in
FIG. 4
is completed.
However, in the conventional TFT array substrate, there are problems as described below.
That is, since the source electrode and the drain electrode are laminates each composed of the barrier metal layer (titanium, molybdenum, or the like) and copper, a cell reaction occurs between the titanium, molybdenum, or the like and the copper when the laminate is etched, and as a result, undercuts in the barrier metal layer are formed at the side surfaces of the pattern. When the undercuts are formed at the above-mentioned location, there are problems with regard to an increase in off-current of the TFT and worsening of residual images. In addition, the wiring widths are difficult to control due to the occurrence of the undercuts in the barrier metal layer, and as a result, there is a problem in that desired characteristics of the TFT cannot be obtained. Furthermore, even though the copper, which is a low resistance material, is used, the barrier metal layer having a higher resistance than that of copper is used as an under layer, and hence, the advantages of copper which has a lower resistance are not sufficiently exploited.
SUMMARY OF THE INVENTION
In order to solve the problems described above, an object of the present invention is to provide a TFT structure and a manufacturing method therefor, in which characteristic defects in the TFT can be prevented, which were caused by undercuts in a barrier metal layer formed in a step for processing a source electrode and a drain electrode composed of copper, and a low resistance wiring can thereby be adequately realized.
To these ends, the TFT of the present invention comprises a gate electrode formed on a substrate, a gate insulation film formed so as to cover the gate electrode, a semiconductor active layer formed on the gate insulation film so as to oppose the gate electrode, ohmic contact layers formed of a doped semiconductor layer and separately formed on two edge portions of the semiconductor active layer, and a source electrode and a drain electrode connected to the semiconductor active layer via
Chul Jo Gyoo
Sung Chae Gee
Booth Richard
Brinks Hofer Gilson & Lione
LG. Philips LCD Co. Ltd.
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