Static information storage and retrieval – Read/write circuit – Particular write circuit
Reexamination Certificate
2011-07-12
2011-07-12
Pham, Ly D (Department: 2827)
Static information storage and retrieval
Read/write circuit
Particular write circuit
C365S158000, C365S171000, C365S173000, C365S209000
Reexamination Certificate
active
07978542
ABSTRACT:
An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.
REFERENCES:
patent: 5748519 (1998-05-01), Tehrani
patent: 5970019 (1999-10-01), Suzuki et al.
patent: 6205071 (2001-03-01), Ooishi
patent: 6256224 (2001-07-01), Perner
patent: 6445613 (2002-09-01), Nagai
patent: 6487108 (2002-11-01), Pochmuller
patent: 6778430 (2004-08-01), Hidaka
patent: 6781874 (2004-08-01), Hidaka
patent: 6788568 (2004-09-01), Hidaka
patent: 2001/0002886 (2001-06-01), Ooishi
patent: 2001/0053091 (2001-12-01), Futatsuya et al.
patent: 2002/0080643 (2002-06-01), Ito
patent: 2002/0176272 (2002-11-01), DeBrosse et al.
patent: 2004/0001351 (2004-01-01), Subramanian et al.
patent: 101 33 646 (2002-04-01), None
patent: 102 15 117 (2002-11-01), None
patent: 102 35 424 (2003-03-01), None
patent: 1 152 430 (2001-04-01), None
patent: 10-106255 (1998-04-01), None
patent: 2002-134708 (2002-05-01), None
patent: 2003-016774 (2003-01-01), None
patent: WO 00/4551 (2000-01-01), None
Itoh et al., “Reviews and Prospects of High-Density RAM Technology”, International Semiconductor Conference Proceedings, vol. 1, Oct. 10 to 14, 2000, p. 13-22.
Scheuelein et al., “A 10 ns. Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell”, IEEE International Solid-State Circuits Conference, Feb. 7-9, 2000, p. 128-129.
Durlam et al., “Non-volatile RAM based on Magnetic Tunnel Junction Elements”, IEEE International Solid-State Circuits Conference, Feb. 7-9, 2000, p. 130-131.
Naji et al., “A 256kb 3.0V 1T1MTJ Non-volatile Magnetoresistive RAM”, IEEE International Solid-State Circuits Conference, Feb. 5-7, 2001, p. 122-123, 438.
Related U.S. Appl. No. 10/189,528, filed Jul. 8, 2002.
Related U.S. Appl. No. 09/805,043, filed Mar. 14, 2001.
Related U.S. U.S. Appl. No. 09/834,638, filed Apr. 16, 2001.
Japanese Office Action, with English Translation, issued in Japanese Patent Application No. JP 2002-288755, mailed Aug. 5, 2008.
McDermott Will & Emery LLP
Pham Ly D
Renesas Electronics Corporation
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