Thin film magnetic memory device with memory cell having...

Static information storage and retrieval – Systems using particular element – Magnetoresistive

Reexamination Certificate

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C365S171000, C365S173000

Reexamination Certificate

active

06958928

ABSTRACT:
In this MRAM device, a memory block is divided into 4 regions, and 4 constant current circuits are respectively provided corresponding to the 4 regions. Bit line drivers select 2 bit lines from each of the 4 regions, that is, 8 bit lines are selected. Bit line drivers supply, to each bit line, an output current from the constant current circuit corresponding to that bit line. Accordingly, a write current flowing through a bit line can be stabilized, and stable data writing can be achieved.

REFERENCES:
patent: 6271710 (2001-08-01), Ooishi
patent: 6611454 (2003-08-01), Hidaka
patent: 6646911 (2003-11-01), Hidaka
patent: 2003/0102901 (2003-06-01), Ooishi
Takeshi Honda, et al. “MRAM-Writing Circuitry to Compensate for Thermal-Variation of Magnetization-Reversal Current” Symposium of VLSI Circuit Digest of Technical Papers (2002).
Roy Scheuerlein et al. “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell” ISSCC Digest of Technical Papers, TA7.2 (Feb. 2000) pp. 94-95, 128-129, 409-410.

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