Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-23
2004-04-13
Ngó, Ngán V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S329000, C257S330000, C257S331000
Reexamination Certificate
active
06720617
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a thin film field effect transistor and a method of its manufacture, aimed at improving the characteristics of the transistor and an integrated circuit utilizing the same.
BACKGROUND OF THE INVENTION
A thin film field effect transistor (FET) typically consists of source and drain electrodes interconnected by semiconductor material. Conduction between the drain and source electrodes occurs basically within the semiconductor, and the length between the source and drain is the conduction channel. Thin film field effect transistors are widely used in systems where it is desirable to have relatively high output currents and high-speed operations referred to as the operating frequency. These two depend largely on the length of the current conduction channel. In particular, the output current is inversely proportional to the channel length, while the operating frequency is inversely proportional to the square of the channel length.
The basic metal-oxide-semiconductor field-effect transistor (MOSFET) structure has a so-called “flat design”, as illustrated in
FIG. 1. A
FET structure
1
is a four-terminal device and consists of a p-type semiconductor substrate
2
, into which two n-regions
3
, a source electrode
4
and drain electrode
5
are formed (e.g., by ion implantation). The metal contact on the insulator is called gate
6
. Heavily doped polysilicon or a combination of silicide and polysilicon can also be used as the gate electrode. The basic device parameters are the channel length L, which is the distance between the two metallurgical n-p junctions, the channel width W, the gate oxide thickness t, the junction depth, and the substrate doping. When voltage is applied to the gate, the source-to-drain electrodes correspond to two p-n junctions connected back to back. The only current that can flow from source to drain is the reverse leakage current. When a sufficiently positive bias is applied to the gate so that a surface inversion layer (or channel) is formed between the two n-regions, the source and the drain are connected by the conducting surface of the n-channel through which a large current can flow. The conductance of this channel can be modulated by varying the gate voltage. This back surface contact (or substrate contact) can have the reference voltage or be reverse-biased: the back surface voltage will also affect the channel conductance.
It is a constant trend of the industry towards higher integration, higher operation frequency, low energy consumption and lower production costs. Those goals were achieved by the constant reduction of the lithographic base line, whose width determines the channel length, the source and drain portals, the conductor's cross-section dimension, and, in brief, the size of the transistor. The gate length determines the frequency or speed of operation, which is strictly dependent on lithographic skill. The state of the art is a line of 180 nm width.
This shrinking in size forced the transistors to be in very close proximity to each other on the flat wafer of silicon. This high density of devices raised some serious problems, including cross-talk between adjacent devices; heating of the chip at operation because of the high frequency along with a high length-to-width ratio of conduction lines and channels; high production costs caused by extremely strict demands for a very clean room and sophisticated photolithography equipment. These problems limit the present fabrication technology.
To solve the above problems, the following solutions were achieved in the art: The use of X-ray or e-beam lithography enables to obtain high integration, however it lacks industrial performance. High frequency is achieved by reducing the gate length with a vertical channel structure. This concept is disclosed in U.S. Pat. Nos. 5,340,759; 5,739,057; 5,780,327; 5.757,038. The best result of about 30 nm gate length can be achieved by the technique disclosed in U.S. Pat. No. 5,757,038, wherein selective wet etching procedures are induced on different semiconductor materials, while the substrate is a semiconductor. By enlarging the width-to-length ratio, low energy consumption can be obtained. This is accomplished by dual gate structure also disclosed in the above patents. The best result for a width-to-length ratio of about 50 can be achieved by the technique disclosed in U.S. Pat. No. 5,757,038. With regard to U.S. Pat. No. 5,340,759, is can be calculated using the parameters indicated therein that this technique could provide an even higher width-to-length ratio (about 80). However, it utilizes a design of silicon wafer on an insulator substrate, and a thin gate channel is produced by an epitaxial process at 750° C. Moreover, Chemical Vapor Deposition is used for applying polysilicon to form a drain layer. The thickness of the thin gate oxide is about 60A.
SUMMARY OF THE INVENTION
There is accordingly a need in the art to improve the manufacture of FET and its structure to provide better operational characteristics of the FET and an electronic circuit utilizing the same.
The present invention provides a FET structure that enables to obtain a larger width-to-length ratio of the semiconductor channel (as compared to the conventional FET structure), having increased operational frequency and low energy consumption. The FET structure of the invention is characterized by sharp-phase edges of p-n junction layers, thereby improving the performance of the semiconductor device. The FET structure enables a significant reduction in cross-talk between two locally adjacent FETs.
A method of manufacturing FETs according to the invention allows for providing a vertically arranged array of FETs, thereby enabling a large number of FETs within the same footprint. The method allows for significantly simplifying the requirements of the manufacture of FET, namely eliminating the need for a “clean room”, allowing low temperature conditions, and reducing the number of fabricating steps.
The main idea of the present invention consists of the following: A FET according to the invention is in the form of a conical-shaped structure, which is made in an insulator layer, and has its tip in contact with a lower electrode (source or drain) layer, preferably located in the interior of this layer. A semiconductor channel is defined by a super structure of semiconductor layers (of n-p-n or p-n-p type), occupying a periphery region of the cone, thereby providing a desirably large width-to-length ratio of the channel. A central region of the cone is a gate electrode on a gate oxide layer. The uppermost electrode (drain or source) is associated with the cone base at least partly covering the uppermost semiconductor layer. The entire FET-structure is surrounded by an insulator.
The FET according to the invention utilizes Semiconductor-on-Insulator or Metal-on Insulator technology to form a structure of the source/drain electrode on an insulator substrate, which is then covered by the insulator layer carrying another layer of active devices.
There is thus provided according to one aspect of the invention, a FET comprising a source electrode, a drain electrode, a gate electrode on a gate oxide, and a semiconductor channel, wherein
a lower one of the source and drain electrodes is formed in a groove made in the surface of an insulator substrate;
the semiconductor channel is defined by a super structure of semiconductor layers located within a periphery region of a conical-shaped structure which is immersed in an insulator layer located above the lower electrode, the tip of the conical-shaped structure being in contact with said lower electrode;
said gate electrode on the gate oxide is located within a central region of said conical-shaped structure; and
the other, upper one of the source and drain electrodes is associated with the base of said conical-shaped structure extending in a plane parallel to said lower electrode.
A plurality of such transistors forming an active layer of second semiconductor devices can be vertically arranged, being sep
Nanogate Ltd.
Ngõ Ngãn V.
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