Thin film field effect element having an LDD structure

Details Thin film field effect element having an LDD structure Thin film field effect element having an LDD structure

1992-07-10

1994-02-01

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257347, 257408, H01L 2976, H01L 2994, H01L 2701, H01L 31062

Patent

active

052834557

ABSTRACT:
An upper insulating layer is formed on an upper surface of a gate electrode formed on an insulating substrate. A gate insulating layer is formed on sidewalls of the gate electrode and the surfaces of the upper insulating layer. A semiconductor layer is formed on the surfaces of the gate insulating layer. Three source/drain regions are formed in the semiconductor layer. Two independent channel regions are formed in the semiconductor layer along both side surfaces of the gate electrode. Source/drain regions are arranged on both ends of two channel regions. Each source/drain region has an LDD structure formed in a self alignment manner by an oblique ion implantation method and a vertical ion implantation method using sidewall insulating layers formed on the channel regions as masks.

REFERENCES:
patent: 4502202 (1985-03-01), Malhi
patent: 4554572 (1985-11-01), Chatterjee
patent: 4555721 (1985-11-01), Bansal et al.
patent: 4980732 (1990-12-01), Okazawa
patent: 5001540 (1991-03-01), Ishihara
patent: 5173754 (1992-12-01), Manning
"Drain-Engineered Hot-Electron-Resistant Device Structures: A Review", J. Sanchez et al, IEEE Transactions of Electron Devices, vol. 36, No. 6, Jun. 1989, pp. 1125-1131.
"1/4 .mu.mLATID (LArge-Tilt-angle Implanted Drain) Technology for 3.3-V Operation", T. Hori, IEDM 89-777-780, 1989.
1984 Symposium on VLSI Technology, Sep. 10-12, 1984, pp. 8-9, Shah et al., "A 2 .mu.m Stacked CMOS 64K SRAM".

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