Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2003-11-04
2004-12-14
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S017000, C438S014000, C438S778000
Reexamination Certificate
active
06830943
ABSTRACT:
TECHNICAL FIELD
The invention described herein relates generally to semiconductor metrology. In particular, the invention relates to methods and standards used for the measurement of very thin gate layers for CMOS devices.
BACKGROUND
Gate dielectric layers (commonly comprised of silicon dioxide and silicon oxynitride materials) are critical components in complementary metal oxide semiconductor (CMOS) devices. As the size and critical dimension of the CMOS devices continues to shrink, the thickness of the gate dielectric layers grows ever thinner. For example, when the length of the gate electrode is on the order of 90 nanometers (nm), the gate layer thicknesses are on the order of about 15 Å thick. In the near future, such gate layers are projected to be 10 Å thick and less. Such thin gate layers pose a number of challenges. Apart from process difficulties, such thin layers challenge the capabilities of metrology tools and standards upon which they are based.
Without reliable calibration standards, it is not possible to have sufficient confidence in the accuracy of semiconductor metrology tools (e.g., X-ray, reflectometers, spectroscopic ellipsometers, discrete wavelength ellipsometers, and the like). Without accurate and reliable measurements and calibration “standards”, semiconductor fabrication is significantly hampered.
“Standards” are simulated semiconductor structures having dimensions similar to those of actual fabricated semiconductor devices. The standards are used to reliably and repeatably calibrate a variety of metrology tools. In turn, the calibrated metrology tools are used to the measure aspects of actual semiconductor devices to determine if they meet with manufacturer specifications.
In order to function effectively as a calibration standard for a semiconductor gate layer, the standard must meet with the following requirements:
(a) be stable against time and temperature;
(b) have a thickness close to that of the desired gate thickness;
(c) be fabricated to a very small tolerance (i.e., having high fabrication reproducibility); and
(d) be useable to calibrate a wide variety of metrology tools.
Existing standards include National Institute of Standards and Technology (NIST) traceable silicon dioxide (SiO
2
) wafers. Also used are SiO
2
layers grown on Si wafers. Although these standards are suitable for many applications, they do not accommodate the needs of measuring ultra-thin film layers. For purposes of this patent, ultra-thin layers shall be defined as layers being less than about 50 Å thick, especially those layers on the order of about 5-30 Å thick.
NIST traceable SiO
2
wafers have SiO
2
layers in excess of 100 Å thick. Such thicknesses make them inapplicable as standards for measurements of ultra-thin films. This is especially so when there is a need to measure gate layers having thicknesses on the order of about 5-30 Å thick. Also, the tolerances in the NIST wafers are on the order of 5-10%. This leads to a variation of at least ±5 Å in the SiO
2
layers. Such variation is drastic in the context of a 5-30 Å thick gate layer. Additionally, the International Technology Roadmap of Semiconductors (ITRS) has provided guidelines for semiconductor fabrication. These guidelines specify that the statistical control limit for variation in gate layer thickness is ±4% of the gate layer thickness. Thus, the existing standards are inadequate for the needs of coming generations of semiconductor devices.
An additional problem is that the SiO
2
layers of NIST traceable SiO
2
wafers are vulnerable to environmental conditions. Even in highly controlled clean-room environments, the SiO
2
layers absorb molecular airborne contaminants (MAC). Such absorption causes significant changes in the thickness of the SiO
2
layers. For example, in a clean-room environment, exposure of NIST traceable SiO
2
wafers to the clean room atmosphere for time periods as short as one hour cause the SiO
2
layer to increase in thickness as much as 0.4 Å. For thicknesses greater than 100 Å, such changes are well within the ITRS guideline and not generally considered significant. However, for ultra-thin films, even this small degree of degradation poses problems. Moreover, such film layer degradation becomes even more significant over time. For example, the SiO
2
layer of the standard can thicken as much as 1.6 Å in a three-month period. Over a nine-month period, the SiO
2
layer of the standard can thicken as much as 3.0 Å. Thus, such a standard would be completely useless as a standard for ultra-thin gate layers (especially for extremely thin 5 Å layers). As a result, such NIST traceable SiO
2
wafers do not meet requirements (a), (b), and (c) above.
Standards using SiO
2
layers grown onto Si wafers also have drawbacks. Although such SiO
2
layers can be grown quite thin, they require extensive fabrication expertise. Additionally, such standards are also vulnerable to environmental conditions and MAC's. As with the NIST standards discussed above, even in highly controlled clean-room environments, the SiO
2
layers absorb MAC's which de grade and thicken their surfaces. Thus, as with NIST standards, they do not meet criteria (a).
What is needed is a standard that is stable over time and under a variety of environmental conditions, has a thickness close to that of the desired gate thickness, can be fabricated to a very small tolerance, have high fabrication reproducibility, and be useable with a wide variety of metrology tools. For these and other reasons, an improved standard is needed.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a calibration standard for use in calibrating semiconductor metrology tools is disclosed.
Embodiments of the invention include a calibration standard having a calibration substrate. A surface of the substrate has a calibration layer formed thereon. A protective layer is then formed over the calibration layer to prevent the deterioration of the underlying calibration layer. The calibration layer and protective layer are formed having thicknesses on the order of thicknesses in actual semiconductor devices to precise tolerances permitting their use as effective calibration standards.
The invention also includes a method for forming a calibration standard for semiconductor metrology tools. Such method comprises providing a substrate having a surface with an rms surface roughness of less than about 1.0 Å. The surface is cleaned and then a calibration layer is formed thereon. The calibration layer is formed having a target thickness of about the same thickness as a layer to be measured on an actual device. A protective layer is formed over the calibration layer to a thickness of about the same as a corresponding layer on the actual device. The protective layer serves, among other things, to protect the calibration layer from deterioration.
These and other aspects of the present invention are described in greater detail in the detailed description of the drawings set forth hereinbelow.
REFERENCES:
patent: 6710889 (2004-03-01), Lee et al.
patent: 2003/0058437 (2003-03-01), Tortonese et al.
Chan David
Lo Wai
Beyer Weaver & Thomas LLP
Lebentritt Michael S.
LSI Logic Corporation
Smith Brad
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