Thin film array panel and manufacturing method thereof

Details Thin film array panel and manufacturing method thereof Thin film array panel and manufacturing method thereof

2004-06-29

2009-11-17

Louie, Wai-Sing (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

C257S072000, C257S083000, C257S290000, C257SE31082

Reexamination Certificate

active

07619249

ABSTRACT:
A method of manufacturing a thin film array panel is provided, which includes: forming a gate line formed on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line and a drain electrode disposed at least on the ohmic contact layer; forming an oxide on the data line; etching the ohmic contact layer using the data line and the drain electrode as an etch mask; and forming a pixel electrode connected to the drain electrode.

REFERENCES:
patent: 5407710 (1995-04-01), Baum et al.
patent: 5784133 (1998-07-01), Kim et al.
patent: 6288414 (2001-09-01), Ahn
patent: 6522370 (2003-02-01), Takahashi et al.
patent: 6630688 (2003-10-01), Kong et al.
patent: 6714269 (2004-03-01), Huang
patent: 6833883 (2004-12-01), Park et al.
patent: 2002/0140034 (2002-10-01), Ahn et al.
patent: 2003/0007106 (2003-01-01), Sakamoto et al.

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