Thin ball grid array package

Details Thin ball grid array package Thin ball grid array package

2002-12-02

2004-08-24

Nhu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S678000

Reexamination Certificate

active

06781242

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to integrated circuit packaging, and more particularly to an improved ball grid array package with low profile and improved thermal and electrical properties.
BACKGROUND OF THE INVENTION
High performance integrated circuit (IC) packages are well known in the art. Improvements in IC packages are driven by industry demands for increased thermal and electrical performance and decreased size and cost of manufacture
In general, array packaging such as Plastic Ball Grid Array (PBGA) packages provide a high density of interconnects relative to the surface area of the package. Typical PBGA packages include a substrate and a semiconductor die attached to the substrate by a die adhesive. Gold wire bonds electrically connect the die to metal traces on the substrate and the wire bonds and die are encapsulated in a molding material. Solder balls are disposed on the bottom surface of the substrate for signal transfer.
While these packages have been widely used, a reduction in package size is desirable in order to keep up with industry demands for decreased size. Also, typical PBGA packages include a convoluted signal path, giving rise to high impedance and an inefficient thermal path, resulting in poor thermal dissipation performance. With increasing package density, the spreading of heat generated by the device is increasingly important.
It is therefore an object of an aspect of the present invention to provide a thin ball grid array package with improved thermal and electrical performance, relative to conventional ball grid array packages.
SUMMARY OF THE INVENTION
In one aspect of the present invention, an integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die is mounted to the heat slug such that at least a portion of the semiconductor die is disposed in the cavity. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate. Bumps of the ball grid array are in electrical connection with ones of the conductive traces.
In another aspect of the present invention, there is provided a process for fabricating an integrated circuit package. The process includes: fixing a heat slug to a substrate having a cavity therein, such that the heat slug spans the cavity; mounting a semiconductor die to the heat slug, at least a portion of the semiconductor die being disposed in the cavity; wire bonding the semiconductor die to ones of conductive traces of the substrate; encapsulating the wire bonds and the semiconductor die in an encapsulating material; and forming a ball grid array on the a first surface of the substrate such that bumps of the ball grid array are in electrical connection with ones of the conductive traces.
In still another aspect of the present invention, an integrated circuit package is provided. The package has a substrate having a first ground on a first surface, a second ground on a second surface, conductive traces extending between the first surface and the second surface, and at least one conductive via extending between the first ground and the second ground. The substrate further has a cavity therein. A heat slug is fixed to the substrate and spans the cavity, such that the heat slug is connected to the first ground. A semiconductor die is mounted to the heat slug, at least a portion of the semiconductor die being disposed in the cavity. A plurality of wire bonds connect the semiconductor die to the second ground and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate, bumps of the ball grid array being in electrical connection with ones of the conductive traces.
Advantageously, the semiconductor die is mounted in the cavity of the substrate, thereby reducing the wire bond length and reducing the package profile in comparison to packages in which the semiconductor die is mounted to a surface of the substrate. In one particular aspect, the die thickness is similar to the substrate thickness. The semiconductor die directly contacts the heat slug, providing efficient thermal dissipation. Also, the heat slug is exposed for mounting to a motherboard to provide further thermal dissipation.
In another aspect, a die adapter is mounted to the surface of the semiconductor die and the encapsulating material surrounds the adapter such that a surface of the adapter is exposed. The adapter provides further thermal dissipation.
In yet another aspect, the semiconductor die is electrically connected to the heat slug through wire bonds, an upper ground ring, connecting vias, and a lower ground ring. The heat slug is exposed for mounting to a motherboard so that the semiconductor die is grounded to the common ground of the motherboard.
In still another aspect, the package is stackable for reduction in motherboard area upon when mounted and to shorten the electrical signal bath between packages, thereby improving package to package communication.


REFERENCES:
patent: 5910686 (1999-06-01), Hanzehdoost et al.
patent: 6175497 (2001-01-01), Tseng et al.
patent: 6184580 (2001-02-01), Lin
patent: 6373131 (2002-04-01), Karnezos
patent: 6414849 (2002-07-01), Chiu
patent: 6537848 (2003-03-01), Camenforte et al.

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