Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-18
2004-08-17
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000, C257S342000
Reexamination Certificate
active
06777747
ABSTRACT:
BACKGROUND
Insulated gate bipolar transistors (IGBTs) are popular control devices for automobile ignition systems. The IGBT can carry large currents with very low resistance and can be rapidly switched on and off with a low voltage gate. They combine the control characteristics of DMOS devices with the current carrying capacity of thyristor.
A typical IGBT is shown in
FIG. 3
a
. Those skilled in the art understand that IGBTs are formed in cellular arrays of sources and bases with emitters. As shown in
FIG. 3
a
, the IGBT
10
has an epitaxial layer
11
that includes N+ source regions
2
surrounded by P-typed base regions
3
. A lightly doped N drift region
5
overlies a heavily doped N buffer region
7
. The epitaxial layer
11
is formed on top of a heavily P doped substrate
9
. On top of the device, a gate insulating layer
17
, typically of silicon dioxide, covers the top of the epitaxial layer
11
. A gate conductive layer, typically polysilicon
19
, covers the insulating layer
17
and forms a gate electrode. Another insulating layer
21
covers the polysilicon and a metal contact layer
23
contacts the source
2
and the base
3
of each cell. The above description is for a planar device with the gate on the surface. However, the IGBT may be fabricated with a trench gate. See
FIG. 3
b.
IGBTs may be used in ignition control circuits such as those showed in
FIGS. 1 and 2
. Those circuits are discussed in this Background portion of the specification in order to explain the invention. The location of that discussion and the discussion itself are not admissions that the circuits are prior art. When the IGBT
10
is on, it drops a low voltage VCE(sat) and current flows through the primary side
12
of transformer
14
. The ratio of the primary to the secondary coil
16
is about 100:1. The voltage is allowed to build to about 400 volts across the primary. When the spark plug is triggered, most of the energy is discharged in the spark. If there is any residual energy, it is dissipated by an auxiliary clamp circuit. In
FIG. 1
the clamp circuit
30
a
is a single pair or multiple pairs of Zener diodes
20
,
22
with a cumulative breakdown voltage of about 400 volts. In
FIG. 2
the clamp circuit
30
b
is a voltage divider including resistors R
1
, R
2
and a single pair or multiple pairs Zener diodes
24
. After the gate signal is removed, auxiliary circuits
30
a
and
30
b
keep the IGBT
10
on in order to dissipate residual energy and prevent a localized failure.
The voltage for the auxiliary circuits
30
a
and
30
b
is set by the zener diodes to dissipate the energy over time. A problem arises if there is no spark due to, for example, a broken spark plug wire or a fouled plug. That leaves an open secondary
16
and the energy remains stored in the inductors
12
,
16
. With the gate turned off, the energy stored in the primary
12
cannot be transferred to the secondary
16
. The primary
16
forces the voltage to rise until the zeners break down. In the self clamped inductive switching (SCIS) mode a portion of the collector current, Izener, is diverted from the collector and into the gate to keep the IGBT on. Then energy stored in the primary inductor
12
will dissipate even after the gate signal is removed.
In the SCIS mode, the IGBT must be capable of absorbing all the energy stored in the ignition coil during abnormal operating conditions. The most common of these abnormal conditions is an open secondary. The N buffer layer
7
plays an important part in the enhancement of the SCIS energy density of IGBT. It is important to minimize the buffer sheet resistance or increase the integrated buffer charge to reduce the parasitic p-n-p current gain &agr;
p-n-p
transistor formed by P Base
3
, N regions
5
,
7
and the P collector
9
. Reducing &agr;
p-n-p
increases the SCIS energy density. The previous generations of IGBT (see
FIGS. 5
,
6
) had relatively thin N buffer regions. For such devices the thinner buffer layer reduced the cost of the starting wafer and, with older deep junction cell technologies, minimized the die size due to increased on-state voltage drop.
More recent devices use designs that have highly reduced on-state voltage drops by using a cellular structure that has shallow planar junctions or trench cellular technologies. Those designs allow the N buffer sheet resistance to be reduced while maintaining an equivalent on-state voltage drop. The newer designs reduce the buffer sheet resistance by: (1) increasing the net peak doping concentration of the buffer and, (2) keeping the buffer thickness the same as previous designs. However, thin buffer regions have several drawbacks. It is often difficult to control their integrated charge. Typical thin buffers are on the order of 12 microns or less. These layers are produced by epitaxial deposition and small errors in epitaxial growth of only a few microns can have dramatic unwanted consequences. Thin layers make it difficult to control the integrated buffer charge or buffer sheet resistance due to out diffusion of the P+ substrate during growth of the epitaxial layer
7
and during high temperature wafer fabrication processing. The migration of P-type dopants from the substrate into the buffer region reduces the desired charge profile of the buffer region.
Characteristics of a conventional design are shown in
FIGS. 5 and 6
. The SCIS capability is directly related to the IGBT parasitic p-n-p current gain &agr;
p-n-p
. That is the gain of regions
3
,
5
/
7
and
9
. The &agr;
p-n-p
determines the level of electron current required to drift through the MOS channel to pass the current during the SCIS clamping phases. The amount of electron current determines how high a voltage level the IGBT gate must be driven to deliver the required the p-n-p base electron current. During SCIS the junction temperature of the IGBT P base increases, thus increasing the level of thermally generated electron leakage current. The leakage current is a another source of p-n-p base current that reduces the amount of electron current to be supplied through the gate controlled MOS channel. If the IGBT is stressed to a high level of SCIS energy, the temperature at the P base junction can reach a level where all the electron current can be supplied by the thermally generated leakage current. At that point the IGBT loses gate control, thermal runaway occurs, and the IGBT clamping function fails. This is further compounded by the fact that the buffer lifetime &tgr;
p
increases as the temperature in the buffer increases due to the thermal transfer of heat from the J
total
·E product. As carrier lifetime increases, there is a corresponding increase in the p-n-p's emitter injection efficiency &ggr;
p-n-p
which in turn increases the gain, &agr;
p-n-p
. Increasing &agr;
p-n-p
results in a lower level of electron current required to drift through the MOS channel to pass the total device current (I
hole
+I
electron
). Thus, the device fails at a lower instantaneous peak junction temperature resulting in a lower SCIS energy density.
FIG. 5
shows the vertical doping, Efield, electron and hole carrier concentration, and the total current density(J
total
) profiles, including the horizontal location of the peak power dissipation during the clamping phase of SCIS for an 8.4 micron thick buffer with an integrated charge of 4.88E+13 a/cm
2
and buffer sheet resistance of 169 &OHgr;/sq. It can be seen that p-n-p emitter injection efficiency &ggr;
p-n-p
is high throughout the buffer and both the electron and hole injected carrier concentrations exceed the peak buffer doping concentration.
FIG. 6
shows the SCIS waveform for a 310 mJ 14.2 A stress for the vertical doping profile of FIG.
5
. The device clamp fails after about 95 &mgr;sec time in clamp and &agr;
p-n-p
=2.52 at the start of SCIS clamping phase.
The silicon area of the IGBT is defined by its SCIS energy density capability. Therefore, it is highly desired that the SCIS energy density(mJ/cm
2
) be increased in order to:
1. Shrink the si
Baran Robert D.
Czeck Bernard J.
Lange Douglas
Wojslawowicz Jack E.
Yedinak Joseph A.
Fairchild Semiconductor Corporation
FitzGerald Esq. Thomas R.
Loke Steven
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