Thevenins receiver

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

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Details

C326S021000, C326S086000, C326S083000, C327S108000, C710S100000

Reexamination Certificate

active

06930507

ABSTRACT:
A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.

REFERENCES:
patent: 5739707 (1998-04-01), Barraclough
patent: 6288564 (2001-09-01), Hedberg
patent: 6347350 (2002-02-01), Muljono
patent: 6429678 (2002-08-01), Wong et al.
patent: 6515502 (2003-02-01), Hsiao et al.
patent: 6556038 (2003-04-01), Kim et al.
patent: 6747475 (2004-06-01), Yuffe et al.

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