Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2005-08-16
2005-08-16
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S021000, C326S086000, C326S083000, C327S108000, C710S100000
Reexamination Certificate
active
06930507
ABSTRACT:
A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.
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Dreps Daniel M.
Ferraiolo Frank D.
Haridass Anand
Truong Bao Gia-Harvey
Frankeny Richard F.
Salys Casimer K.
Tan Vibol
Winstead Sechrest & Minick P.C.
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