Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2000-11-13
2002-06-04
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S718000
Reexamination Certificate
active
06400013
ABSTRACT:
BACKGROUND ART
1. Field of the Invention
The present invention relates to a thermoelectric module and a method of fabricating the thermoelectric module having a matrix of series connected thermoelectric chips for use in a heat-exchange system.
2. Description of the Prior Art
WO 97/45882 discloses a prior thermoelectric module having a matrix of thermoelectric chips which are arranged between a set of first contacts and a set of second contacts to form a series electric circuit. The circuit is composed of a plurality of linear arrays each having a limited number of the chips of P-type and N-type arranged alternately along a column of the matrix and are bonded on one face of the chips to the individual first contacts and bonded on the opposite face to the individual second contacts. The two adjacent first contacts in each linear array are connected to form first discrete couples, while the two adjacent second contacts are likewise connected to form second discrete couples. Thus, the chips in the individual linear arrays are connected in series to form sub-circuits. The sub-circuits are electrically interconnected by means of first and second inter-array bridges which are formed respectively on the sides of the first and second contacts to extend across the two first and second contacts of the adjacent linear arrays, respectively. Thus, the chip at one end of the linear array is restricted on its one side by the first or second couples in the single array and also restricted on the opposite side by the second or first inter-array bridges extending across the two adjacent arrays.
Generally, the thermoelectric module is utilized with the set of the first contacts rigidly mounted on a supporting structure and with the set of the second contacts in rather soft contact with a heating or cooling member. Therefore, heat stress developed at the individual chips during the use is better to be relieved on the side of the second contacts rather than on the side of the first contacts rigidly mounted on the supporting structure. Nevertheless, the presence of the second inter-array bridge utilized in the above prior art becomes a certain hindrance to relieving the heat stress on the side of the second contacts. That is, the adjacent arrays or sub-circuits of the chips are restricted to each other by the second inter-array bridge so that heat stress is difficult to be relieved on the side of the second contacts, thereby sometimes resulting in undesired fracture or crack in the chip at the end of the array which is restricted on the opposite sides thereof in the two different directions one along the individual array and the other crossing therewith.
SUMMARY OF THE INVENTION
The present invention has been accomplished in view of the above problem and has a primary object of providing an improved thermoelectric module which is capable of successfully reducing the heat stress for increased reliability. The thermoelectric module in accordance with the present invention includes a plurality of thermoelectric chips of P-type and N-type arranged in a matrix between a set of first contacts and a set of second contacts to form a series connected electrical circuit which is adapted to flow an electric current therethrough for heating one side of the first and second contacts while cooling the other side of the first and second contacts due to the Peltier effect at the chips. The chips are arranged to give at least three chip arrays each having a limited number of the chips. A first carrier is provided on one side of the chips to carry the set of the first contacts and to include first bridges each integrally joining two adjacent first contacts to define first discrete couples for electrical connection of the chips in each chip array. The first carrier further includes at least two inter-array bridges which are solely responsible for electrical interconnection between the adjacent chip arrays. The first carrier is fixedly mounted on a rigid substrate so as to restrain the first discrete couples on the substrate. On the opposite side of the chips, there are formed a plurality of second bridges each integrally joining the two adjacent second contacts to give second discrete couples for electrical connection of the two adjacent chips in each of the chip arrays. With this structural arrangement, the inter-array bridges are formed only on one side of the chips for interconnection of the first contacts between the adjacent chip arrays, while the second contacts are distributed on the other side of the chips as second discrete couples. Thus, the heat stress applied to the end of the chip array where the two adjacent chip arrays are interconnected can be well relieved on the side of the second contacts in which the second discrete couples are kept totally isolated from each other.
Accordingly, it is a primary object of the present invention to provide a thermoelectric module which is capable of relieving the heat stress developed in the chips during the use to give a fracture-free rugged structure.
In one preferred embodiment, each chip array is defined by the chips, the first contacts, and the second contacts all arranged along each column of the matrix. The first bridges are first vertical bridges each integrally joining the two adjacent first contacts in each column to give the first discrete couples. The inter-array bridges are formed to join the two adjacent first contacts in the outermost rows of the matrix to form horizontal couples for electrical interconnection between the adjacent chip arrays. The second bridges are in the form of second vertical bridges each integrally joining the two adjacent second contacts in each column of the matrix to give the second discrete couples so that the second discrete couples arranged along one column of the matrix are uniformly staggered with respect to the second discrete couples arrange along the adjacent column of the matrix.
In another preferred embodiment of the present invention, each chip array is defined by the chips arranged in a pair of the two adjacent rows of the matrix, the first contacts in the corresponding two adjacent rows of matrix, and the second contacts in the corresponding two adjacent rows of matrix. The first bridges are in the form of first oblique bridges each integrally joining a pair of two obliquely opposed first contacts, one in the one row and the other in the adjacent row to give the first discrete couples. The inter-array bridges are provided to join a pair of two vertically opposed first contacts, one in the row of the chip array and the other in the row of the adjacent chip array for electrical interconnection between the adjacent chip arrays. The second bridges are in the form of second vertical bridges each integrally joining the two adjacent second contacts in each column of the matrix to give the second discrete couples which are aligned along the columns as well as along the rows of the matrix. With this arrangement, the chips of the P-type and N-type can be arranged alternately along the entire length of the series circuit over the plural chip arrays without leaving no duplicate couples of the same type at the connection between the chip arrays, thereby providing a tight distribution of the chip within a limited space for improved heat-transfer efficiency.
The present invention also provides an improved method of fabricating the thermoelectric module. The method utilizes a plurality of thermoelectric bars of P-type and N-type to be subsequently separated into the thermoelectric chips, a first carrier carrying the set of first contacts, and a second conductive plate carrying the set of the second contacts. The first carrier includes the first bridges forming the first discrete couples, and includes at least two inter-array bridges which are solely responsible for electrical interconnection between the adjacent chip arrays. The second conductive plate includes the second bridges defining the second discrete couples, and includes the second beams which integrally connect the second discrete couples in order that all of the second
Imai Junji
Inoue Hiroyuki
Iwamoto Narimasa
Komatsu Teruaki
Maekawa Nobuteru
Matsushita Electric & Works Ltd.
Potter Roy
Rader & Fishman & Grauer, PLLC
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