Thermally enhanced stacked die package

Details Thermally enhanced stacked die package Thermally enhanced stacked die package

2003-02-06

2003-09-30

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With provision for cooling the housing or its contents

C257S723000

Reexamination Certificate

active

06627990

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to electronic packaging and specifically to stacked die/chip packages.
BACKGROUND OF THE INVENTION
Current practice involves using solid element spacers between stacked dies/chips. Such spacers are typically comprised of organic adhesive alone or in combination with ceramic/silicon. However, the top die/chip has been found to have thermal issues. The solid element spacers cannot be comprised of electrically conductive material and such solid element spacers generally have low thermal conductivity.
U.S. Pat. No. 6,261,865 B1 to Akram describes a multi-chip semiconductor package using a lead-on-chip lead frame and method of construction.
U.S. Pat. No. 6,087,722 to Lee et al. describes a multi-chip package that does not include a die pad.
U.S. Pat. No. 6,118,176 to Tao et al. describes a stacked chip assembly generally includes a first chip, a second chip and a lead frame.
U.S. Pat. No. 6,297,547 B1 to Akram describes a multiple die package in which a first and second die are mounted on a leadframe.
U.S. Pat. No. 5,814,881 to Alagaratnam et al. describes a stacked integrated chip package and method of making same.
U.S. Pat. No. Re. 36,613 to Ball describes a multiple stacked die device that contains up to four dies and permits close-tolerance stacking by a low-loop-profile wire-bonding operation and a thin-adhesive layer between the stacked dies.
U.S. Pat. No. 6,080,264 to Ball describes an apparatus and method for increasing integrated circuit density comprising utilizing chips with both direct (flip chip type) chip to conductors connection technology and wire bonds and/or tape automated bonding (TAB).
U.S. Pat. No. 6,087,718 to Cho describes a stacked-type semiconductor chip package of a lead-on chip structure which is modified for stacking chips in the package.
U.S. Pat. No. 6,307,257 B1 to Huang et al. describes a dual-chip integrated circuit (IC) package with a chip-die pad formed form leadframe leads.
U.S. Pat. No. 6,337,521 B1 to Masuda describes a semiconductor device and a method of manufacturing the same. The device comprising two semiconductor chips stacked on each other with their backs opposite to each other and sealed with a mold resin.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide thermally enhanced stacked die/chip package designs.
Another object of one or more embodiments of the present invention to provide stacked die/chip package designs having reduced die attach interface area to reduce stress and moisture sensitivity.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a stacked die design, and a method of forming the same, comprising: a substrate having a lower surface and an upper surface; a lower die connected to the substrate; a thermally conductive metal interposer thermally connected to the substrate; and an upper die thermally connected to the metal interposer. The lower die and the upper die being spaced apart and comprising a stacked die whereby any heat generated by the upper die is transferred to the substrate by the metal interposer.


REFERENCES:
patent: 5814881 (1998-09-01), Alagaratnam et al.
patent: 6080264 (2000-06-01), Ball
patent: 6087718 (2000-07-01), Cho
patent: 6087722 (2000-07-01), Lee et al.
patent: 6118176 (2000-09-01), Tao et al.
patent: 6261865 (2001-07-01), Akram
patent: 6297547 (2001-10-01), Akram
patent: 6307257 (2001-10-01), Huang et al.
patent: 6337521 (2002-01-01), Masada

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