Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2000-09-21
2004-08-03
Clark, Sheila V. (Department: 2815)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C257S707000
Reexamination Certificate
active
06770513
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor packaging. More particularly, a packaging arrangement that utilizes a metallic solder material to couple the back side of a flip chip device to a heat sink is described.
As semiconductor manufacturing techniques improve, the size of semiconductor devices tends to decrease and the density of components within such devices tends to increase. One drawback of such trends is that in more complex and/or high power devices they increase the need to manage the dissipation of the heat generated during operation. One conventional approach to heat management is to glue a metallic heat sink to the die. Most commonly the heat sinks are formed from anodized aluminum, although other materials are used as well. By way of example and referring to
FIG. 1
, in flip chip packaging it is common to use an epoxy adhesive
23
to couple a heat sink
20
to the back side of a flip chip die
25
. Although such an arrangement works well in many circumstances, most epoxy adhesives have relatively low thermal conductivities. The low thermal conductivity of the epoxy adhesive thus becomes a significant limitation to the overall effectiveness of the heat sink.
Another conventional flip chip packaging arrangement is illustrated in FIG.
2
. In this embodiment, a flip chip type die
45
is mounted on a ball or pin grid array substrate
48
in a conventional manner. A heat sink
50
having a ring foot
52
is then secured to the substrate
48
. More specifically, the ring foot
52
portion of the heat sink is adhered to the substrate using an appropriate adhesive material such as epoxy. A thermal grease
54
is then typically used to improve the thermal contact between the die
45
and the heat sink
50
. However, like the epoxy adhesives used to attach a heat sink directly to a die, conventional thermal greases used in semiconductor packaging applications tend to have relatively low thermal conductivities. Thus again, the relatively low thermal conductivity of the thermal grease becomes a significant limitation to the overall effectiveness of the heat sink.
Although the flip chip packaging arrangements described above work well in many applications, there is a continuing need for improved flip chip style packaging arrangements that facilitate better heat dissipation.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, an improved arrangement for attaching a heat sink to a flip chip type die is disclosed. More specifically, the heat sink is attached to the back surface of the flip chip die by a metallic solder material. Such an arrangement provides good thermal conductivity between the die and the heat sink. In some embodiments, the die is mounted on a grid array type substrate in a flip chip arrangement such that the die's contacts are coupled to adjacent I/O pads on the substrate.
In some embodiments, one or more metallic intermediate die attach layers are deposited over the back surface of the die to form a solderable die surface. The heat sink is then attached to the solderable die surface. This approach works well when the chosen solder does not adhere well to the semiconductor die material. In one preferred implementation the intermediate metallic layers include a barrier layer that is deposited over the back surface of the die and a solderable metallic layer that is deposited over the barrier layer. The barrier layer is typically used to prevent undesirable interactions between the solderable metallic layer and the semiconductor material and/or to improve adhesion of the solderable layer, to the semiconductor material. In a method aspect, the barrier and metallic layers may be deposited on the back side of a wafer during fabrication which provides the desired structure after dicing.
REFERENCES:
patent: 4499659 (1985-02-01), Varteresian et al.
patent: 4620215 (1986-10-01), Lee
patent: 5533256 (1996-07-01), Call et al.
patent: 5843808 (1998-12-01), Karnezos
patent: 5903437 (1999-05-01), Pierson et al.
patent: 6046498 (2000-04-01), Yoshikawa
patent: 6046907 (2000-04-01), Yamaguchi
patent: 6084775 (2000-07-01), Bartley et al.
patent: 6091603 (2000-07-01), Daves et al.
patent: 6111322 (2000-08-01), Ando et al.
patent: 6262489 (2001-07-01), Koors et al.
patent: 6275381 (2001-08-01), Edwards et al.
patent: 6281575 (2001-08-01), Nishikawa et al.
patent: 6292369 (2001-09-01), Daves et al.
Schaefer William J.
Vikram Seshadri
Beyer Weaver & Thomas LLP
Clark Sheila V.
National Semiconductor Corporation
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