Thermally enhanced chip scale lead on chip semiconductor...

Details Thermally enhanced chip scale lead on chip semiconductor... Thermally enhanced chip scale lead on chip semiconductor...

2006-06-20

2006-06-20

Owens, Douglas W. (Department: 2811)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S123000

Reexamination Certificate

active

07064009

ABSTRACT:
A thermally enhanced, chip-scale, Lead-on-Chip (“LOC”) semiconductor package includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink. The lands can be connected to selected ones of the lead fingers, and/or combined with one another for even greater thermal and electrical conductivity.

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