Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-10-10
2004-10-26
Gibson, Randy W. (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S712000, C361S779000, C361S762000, C257S698000, C257S778000, C174S259000, C174S260000
Reexamination Certificate
active
06809935
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of eliminating the thermal mismatch between silicon and a Printed Circuit Board substrate.
(2) Description of the Prior Art
Semiconductor device performance improvements are largely achieved by reducing device dimensions, a development that has at the same time resulted in considerable increases in device density and device complexity. These developments have resulted in placing increasing demands on the methods and techniques that are used to access the devices, also referred to as I/O capabilities of the device. This has led to new methods of packaging semiconductor devices whereby structures such as Ball Grid Array (BGA) devices and Column Grid Array (CGA) devices have been developed A Ball Grid Array (BGA) is an array of solderable balls placed on a chip carrier. The balls contact a printed circuit board in an array configuration where, after reheat, the balls connect the chip to the printed circuit board. BGA's are known with 40, 50 and 60 mils. spacings in regular and staggered array patterns. Due to the increased device miniaturization, the impact that device interconnects have on device performance and device cost has also become a larger factor in package development. Device interconnects, due to their increase in length in order to package complex devices and connect these devices to surrounding circuitry, tend to have an increasingly negative impact on the package performance. For longer and more robust metal interconnects, the parasitic capacitance and resistance of the metal interconnection increase, which degrades the chip performance significantly. Of particular concern in this respect is the voltage drop along power and ground buses and the RC delay that is introduced in the critical signal paths. In many cases the requirements that are placed on metal interconnects results in conflicting performance impacts. For instance, attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires. It is therefore the trend in the industry to look for and apply metals for the interconnects that have low electrical resistance, such as copper, while at the same time using materials that have low dielectric materials for insulation between interconnecting lines.
One of the more recent developments that is aimed at increasing the Input-Output (I/O) capabilities is the development of Flip Chip Packages. Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads on a semiconductor device, the bumps are interconnected directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest path. This technology can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger while more sophisticated substrates can be used that accommodate several chips to form larger functional units.
The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and TCE (Temperature Coefficient of Expansion) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder-lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations.
In general, Chip-On-Board (COB) techniques are used to attach semiconductor die to a printed circuit board, these techniques include the technical disciplines of flip chip attachment, wirebonding, and tape automated bonding (TAB). Flip chip attachment consists of attaching a flip chip to a printed circuit board or to another substrate. A flip chip is a semiconductor chip that has a pattern or arrays of terminals that is spaced around an active surface of the flip chip that allows for face down mounting of the flip chip to a substrate.
Generally, the flip chip active surface has one of the following electrical connectors: BGA (wherein an array of minute solder balls is disposed on the surface of the flip chip that attaches to the substrate); Slightly Larger than Integrated Circuit Carrier (SLICC) (which is similar to the BGA but having a smaller solder ball pitch and diameter than the BGA); a Pin Grid Array (PGA) (wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip, such that the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto. With the BGA or SLICC, the solder or other conductive ball arrangement on the flip chip must be a mirror image of the connecting bond pads on the printed circuit board so that precise connection can be made. The flip chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror image of the recesses on the printed circuit board. After insertion, soldering the pins in place generally bonds the flip chip.
A Prior Art method of packaging a BGA chip is shown in FIG.
1
. The BGA chip
11
is mounted in a cavity
18
that is provided in the surface of a BGA substrate or a substrate
10
, substrate
10
has a surface that is electrically conductive. The BGA chip
11
is centered with respect to the substrate
10
, whereby the contact points of the semiconductor device
11
are closely spaced around the periphery of the die
11
. Cavity
18
is provided in the substrate
10
for the mounting of the Integrated Circuit (IC) chip
11
. The top surface of the IC chip
11
is in close physical contact with the substrate
10
via a thin adhesive layer
15
, typically of thermally conductive epoxy, that is deposited over the top surface of cavity
18
. The IC die
11
is attached to the substrate
10
by means of this layer
15
, providing a path of heat conductivity between the semiconductor die.
11
and the substrate
10
. The adhesive layer
15
is cured after the IC die
11
has been inserted into cavity
18
. The contact points of the die
11
are conductively bonded, using wire-bonding techniques, to the substrate layer
19
.
The bond wires
12
are shown here as applied for the connection of the IC die
11
to a top layer
13
of an interconnect substrate
19
. The interconnect substrate
19
can contain multiple layers of interconnect lines and contact pads. The interconnect substrate
19
is connected to the underlying substrate
10
by means of layer
16
, which is typically a layer of adhesive material. This establishes the necessary mechanical support for the wire bonding operation. The interconnect substrate
19
can further contain a mechanical stiffener to provide rigidity to the interconnect substrate
19
. The upper layer of the interconnect substrate
19
contains (metal, for instance copper) traces
13
to which contact balls (not shown in
FIG. 1
) can be connected for further interconnects to surrounding circuitry or functional elements. Wires
12
provide a wire bond connection between contact points on the surface of the IC die
11
and copper traces
14
that are part of the interconnect substrate
19
. For the connection of the upper layer of the interconnect substrate
19
to connecting solder balls, a solder mask layer (not shown in
FIG. 1
) with openings is deposited over the surface of the substrate layer
19
. The openings that are created in the solder mask provide solder connections between the metal traces
13
and the contact balls.
FIG. 1
also shows how the IC die
11
is encapsulated using an encapsulation material that is syringe dispensed to surround the die
11
forming the encapsulation layer
17
. It must
Ackerman Stephen B.
Bui Hung
Gibson Randy W.
Megic Corporation
Pike Rosemary L. S.
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