Thermal treatment process for forming thin film transistors...

Details Thermal treatment process for forming thin film transistors... Thermal treatment process for forming thin film transistors...

2001-04-20

2003-04-15

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S308000, C438S378000, C438S166000

Reexamination Certificate

active

06548332

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a process for forming a thin film transistor (TFT), and more particularly to a process for forming a thin film transistor used in a liquid crystal display (LCD).
BACKGROUND OF THE INVENTION
Presently, the traditional picture tube display is gradually replaced because of the hung volume thereof and the radiation. The potential replacer is the liquid crystal display because the advantages of power-saving and easy carrying are achieved by using the liquid crystal display. Therefore, the liquid crystal display becomes the basic equipment for the notebook. Also, the liquid crystal display becomes the main stream of the table directive view plane display for applying to personal computers, video games, and monitors. Therefore, the liquid crystal display will be the leading product in the future.
Generally, most liquid crystal displays are manufactured by using the thin film transistors as driving devices, so that the output property of the thin film transistor affects the performance of the liquid crystal display mostly. Therefore, it is indeed an important issue to improve the process and the property of the thin film transistor.
FIGS. 1A-1E
are schematic sectional views illustrating a method for forming a thin film transistor according to the prior art. As shown in
FIG. 1A
, a gate
11
a
is formed on a substrate
10
by two steps: (1) forming a conducting layer on the substrate
10
, and (2) removing the conducting layer which is not located at the gate region by photolithography and etching for forming the gate
11
a
. Sequentially, a gate dielectric layer
12
and an amorphous silicon layer
13
are in order formed on the gate
11
a
and the amorphous silicon layer
13
is further formed into an amorphous silicon island as shown in
FIG. 1B
by photolithography and etching. Then, a doped amorphous silicon layer
15
and a metal layer
16
are in order formed on the gate dielectric layer
12
, as is shown in FIG.
1
C.
Referring to
FIG. 1D
, portions of the doped amorphous silicon layer
15
and the metal layer
16
are removed by photolithography and etching for forming a source
15
a
, a drain
15
b
, a source electrode
16
a
, and a drain electrode
16
b
, respectively. Sequentially, a passivation
17
is formed on portions of the gate dielectric layer
12
and the amorphous silicon island
13
, the source electrode
16
a
, and the drain electrode
16
b
. The passivation
17
located on the drain electrode
16
b
is partially removed to form a contact window
19
. Then, a transparent conducting later
18
is formed in the contact window
19
and on the passivation
17
. After photolithography and etching, a pixel electrode
18
a
is formed as shown in FIG.
1
E. Finally, after an annealing step for stabilizing the structure and modifying the crystallization and interface property thereof, the finished traditional structure of the thin film transistor is formed.
During the period of etching the doped amorphous silicon layer
15
and the metal layer
16
, a portion of amorphous silicon layer
13
is also etched, which causes the amorphous silicon layer
13
becomes thinner. Thus, an etching stop layer whose composition is silicon nitride is generally formed on the amorphous silicon layer
13
by a plasma enhanced chemical vapor deposition (PECVD) for forming an etching stop thin film transistor.
FIGS. 2A-2F
illustrate a method for forming the etching stop thin film transistor according to the prior art. First of all, a gate
11
a
is formed on a substrate
10
as shown in FIG.
2
A. Sequentially, a gate dielectric layer
12
, an amorphous silicon layer
13
, and an insulating layer
14
which is a silicon nitride are in order formed on the substrate
10
and the gate
11
a
(see FIG.
2
B). Then, a portion of insulating layer
14
is removed by photolithography and etching for forming the etching stop layer
14
a
as shown in FIG.
2
C. Sequentially, as shown in
FIG. 2D
, a doped amorphous silicon layer
15
and a metal layer
16
are in order formed on the amorphous silicon layer
13
and the etching stop layer
14
a.
FIG. 2E
illustrates that portions of the amorphous silicon layer
13
, the doped amorphous silicon layer
15
, and the metal layer
16
are removed by photolithography and etching for forming a source
15
a
, a drain
15
b
, a source electrode
16
a
, and a drain electrode
16
b
. In this step, the amorphous silicon layer
13
is protected from etching owing to the etching stop layer
14
a
. Then, a passivation
17
is formed on portions of the gate dielectric layer
12
, the etching stop layer
14
a
, the source electrode
16
a
, and the drain electrode
16
b
. Sequentially, the passivation
17
located on the drain electrode
16
b
is partially removed to form a contact window. Then, a transparent conducting layer is formed in the contact window and on the passivation
17
. After photolithography and etching, a pixel electrode
18
a
is formed as shown in FIG.
2
F. Finally, after an annealing step for stabilizing structure and modifying the crystallization and interface property thereof, a finished traditional structure of etching stop thin film transistor is formed.
However, the source
15
a
and the drain
15
b
are locates on the opposite side of the etching stop layer
14
a
, so that they can be a switch of the amorphous silicon layer
13
for generating the effect of a parasitic transistor. The effect of parasitic transistor results in a double hump phenomenon in the output property plot of the thin film transistor as shown in FIG.
3
.
FIG. 3
is a diagram illustrating the relation between the gate voltage and the drain current. When the gate of thin film transistor is applied a voltage, the current passing through the drain has a two-staged change in the linear region, or even a three-staged change called the triple hump phenomenon. Thus, it is impossible to clearly define the switch status, i.e. “on” or “off”, of the thin film transistor, which is a serious defect of the thin film transistor as a driving device. In addition, while the interface properties of the etching stop layer
14
a
and those of the amorphous silicon layer
13
are not matched, or the device is damaged by plasma during etching the doped amorphous silicon layer
15
and the insulating layer
14
, the problems of increasing the closing current, increasing the threshold voltage, decreasing the sub-threshold swing are occurred.
Currently, some methods have been developed for the thin film transistor to avoid the above undesired properties. One is that after forming the structure of the gate, the amorphous silicon layer, the source and the drain, the structure is treated by plasma before forming the passivation and the pixel electrode. Another is that after forming the amorphous silicon layer, the structure is treated by a first plasma treatment which infuses the decomposed ion into the amorphous silicon layer by a high energy plasma for filling the dangling bond. The other is similar with the previous one except after forming the passivation and the conducting electrode, the thin film transistor is treated by a H
2
O plasma. However, it is not only cost but also decreasing yield because of adding one or two steps of plasma treatment. In addition, the distribution of the plasma naturally cannot even, so it is hard to control in the large area process.
Besides the etching stop thin film transistor, the back channel etched thin film transistor is another general type. The process for producing the back channel etched thin film transistor is the same as that of the etching stop thin film transistor shown in
FIGS. 1A-1E
. After forming the source
15
a
and the drain
15
b
, the amorphous silicon layer
13
is exposed to the passivation
17
. The exposed portion of the amorphous layer
13
will produce the interface defect because of the plasma erosion or the different silicon composition of the passivation
17
. Thus, if the interface status is controlled improperly, the bad output property of the thin film transistor coul

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