Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-04
2002-05-07
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S299000, C438S581000, C438S583000, C438S630000, C438S649000, C438S651000, C438S661000, C438S664000
Reexamination Certificate
active
06383922
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a thermally stable cobalt silicide film in the fabrication of integrated circuits.
(2) Description of the Prior Art
Cobalt disilicide (CoSi
2
)is a preferred salicide technology as CMOS device sizes shrink to 0.18 &mgr;m and beyond because of its good performance with small polysilicon and active area line widths. Cobalt disilicide also has been widely accepted in deep sub-micron devices to reduce the contact resistance. As device scales shrink further and molecular processes evolve, the requirement for cobalt disilicide film properties becomes more stringent. One of the concerns over the cobalt disilicide (CoSi
2
) film properties is its thermal stability. It is known that the thermal stability of CoSi
2
is thickness dependent. That is, the thinner the CoSi
2
film, the more thermally unstable it becomes. The sheet resistance of the thin CoSi
2
film could be increased significantly when it experiences a thermal stress in subsequent processing. On the other hand, for shallow junctions, the CoSi
2
, thickness must be decreased. Thus, the CoSi
2
film thermal stability for thin films must be improved.
A number of patents disclose methods of forming CoSi
2
. U.S. Pat. No. 6,022,457 to Huang et al discloses cleaning the native oxide layer off the silicon substrate, then depositing a titanium layer under the cobalt layer. A silicon layer may be deposited over the titanium layer and under the cobalt layer. A RTA process forms CoSi
2
. U.S. Pat. No. 6,083,817 to Nogami et al teaches a tungsten nitride capping layer over the cobalt layer. U.S. Pat. No. 6,025,267 to Pey et al discloses a titanium nitride layer over the cobalt. U.S. Pat. No. 5,869,396 to Pan et al shows a method of forming cobalt disilicide.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a cobalt disilicide film in the fabrication of an integrated circuit.
A further object of the invention is to provide a method of fabricating a thermally stable cobalt disilicide film in the fabrication of an integrated circuit.
Yet another object is to provide a method of forming a thermally stable cobalt disilicide film by using a titanium stuffing technique.
In accordance with the objects of the invention a method for forming a thermally stable cobalt disilicide film in the fabrication of an integrated circuit is achieved. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the silicon regions to be silicided. A capping layer is deposited overlying the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. A titanium layer is deposited overlying the cobalt monosilicide layer. Thereafter the substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide. During this transformation, some titanium atoms diffuse into and are incorporated into the cobalt disilicide film. The titanium layer is removed to complete formation of a thermally stable cobalt disilicide film in the manufacture of an integrated circuit.
REFERENCES:
patent: 5869396 (1999-02-01), Pan et al.
patent: 6022457 (2000-02-01), Huang et al.
patent: 6025267 (2000-02-01), Peg et al.
patent: 6083817 (2000-07-01), Nogami et al.
patent: 6274470 (2001-08-01), Ichimori et al.
Sohn et al, “High Thermal Stability and Low Junction Leakage Current of Ti Capped Co salicide and its Feasibility for High Thermal Budget CMOS devices”, Electron Device Meeting, 1998, IEDM's 98 Technical Digest, Internation, Dec. 6, 1998, pp. 1005-1008.
Ang Arthur
Chew Peter
Lai Chung Woh
Lim Eng Hua
Zhang Bei Chao
Chartered Semiconductor Manufacturing Ltd.
Chaudhari Chandra
Pham Thanhha
Pike Rosemary L. S.
Saile George O.
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