Thermal spacer for stacked die package thermal management

Details Thermal spacer for stacked die package thermal management Thermal spacer for stacked die package thermal management

2010-03-26

2011-12-27

Wilczewski, Mary (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

C257S686000, C257S707000, C438S127000, C438S122000, C438S124000

Reexamination Certificate

active

08084856

ABSTRACT:
In some embodiments, a thermal spacer for stacked die package thermal management is presented. In this regard, an apparatus is introduced having a top integrated circuit die, a bottom integrated circuit die, and a thermal spacer between the top and bottom integrated circuit dice, the thermal spacer comprising a heat conducting material and the thermal spacer overhanging and extending parallel with one outside edge of the bottom integrated circuit die. Other embodiments are also disclosed and claimed.

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Yamada et al., “The Study of Silicon Dies Stress In Stacked Die Packages”, Dec. 2005, International Symposium on Electronics Materials and Packaging, Dec. 11-14, 2005, pp. 74-77.
Akhter et al., “Design for Stackability of Flash Memory Devices Based on Thermal Optimization”, The 24th Digital Avionics Systems Conference, Oct. 30-Nov. 3, vol. 2, 2005, pp. 9.C.1-1 to 9.C.1-14.

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