Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-10-19
2001-05-29
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S427000
Reexamination Certificate
active
06239002
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to ozone-TEOS thermal chemical vapor deposition (CVD) methods for forming within microelectronics fabrications silicon oxide dielectric layers. More particularly, the present invention relates to ozone-TEOS thermal chemical vapor deposition (CVD) methods for forming within microelectronics fabrications silicon oxide dielectric layers formed with attenuated surface sensitivity with respect to thermal silicon oxide substrate layers.
2. Description of the Related Art
Integrated circuit microelectronics fabrications are formed from semiconductor substrates within and upon which are formed integrated circuit devices. The integrated circuit devices are connected internally and externally to the semiconductor substrates upon which they are formed through patterned integrated circuit conductor layers which are separated by integrated circuit dielectric layers.
As integrated circuit microelectronics fabrication integration levels have increased and integrated circuit device and patterned conductor layer dimensions have decreased, it has become more prevalent in the art of integrated circuit microelectronics fabrication to employ trench isolation methods, such as but not limited to shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods, to form trench isolation regions within a semiconductor substrate in order to separate active regions of the semiconductor substrate within and upon which are formed integrated circuit devices.
Such shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are desirable within integrated circuit microelectronics fabrications since shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods provide trench isolation regions which are nominally co-planar with a surface of an adjoining active region of a semiconductor substrate. Such nominally co-planar trench isolation regions and adjoining active regions of a semiconductor substrate generally optimize an attenuated depth of focus typically achievable with an advanced photoexposure apparatus employed when forming advanced integrated circuit microelectronics devices and advanced patterned conductor layers within an advanced integrated circuit microelectronics fabrication.
While shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are thus desirable when forming trench isolation regions within advanced integrated circuit microelectronics fabrications, shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are nonetheless not entirely without problems within advanced integrated circuit microelectronics fabrications. In particular, it is often difficult to form when employing shallow trench isolation (STI) methods within integrated circuit microelectronics fabrications shallow trench isolation (STI) regions which simultaneously possess superior gap filling properties, superior bulk physical properties and enhanced deposition rates which in the aggregate provide shallow trench isolation regions with optimal properties within advanced integrated circuit microelectronics fabrications.
Of the dielectric layer deposition methods potentially applicable for forming shallow trench isolation regions when employing shallow trench isolation (STI) methods within integrated circuit microelectronics fabrications, atmospheric pressure thermal chemical vapor deposition (APCVD) methods and sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods employing ozone as an oxidant source material and tetraethylorthosilicate (TEOS) as a silicon source material (hereinafter, in general, “ozone-TEOS thermal chemical vapor deposition (CVD) methods”) are particularly desirable due to the superior gap tiling properties of shallow trench isolation regions formed employing those ozone-TEOS thermal chemical vapor deposition (CVD) methods. Such ozone-TEOS thermal chemical vapor deposition (CVD) methods typically preclude plasma activation due to the increased reactor chamber pressures at which they are undertaken. While ozone-TEOS thermal chemical vapor deposition (CVD) methods do typically provide shallow trench isolation regions formed with superior gap filling properties, ozone-TEOS therm chemical vapor deposition (CVD) methods typically nonetheless also typically provide shallow trench isolation regions with inferior bulk properties (as typically evidenced by increased aqueous hydrofluoric acid etch rate) and with attenuated deposition rates upon thermal silicon oxide trench liner layers formed through thermal oxidation of silicon semiconductor substrates within which are formed those shallow trench isolation regions employing those ozone-TEOS thermal chemical vapor deposition (CVD) methods.
It is thus towards the goal of forming within integrated circuit microelectronics fabrications shallow trench isolation regions while employing ozone-TEOS thermal chemical vapor deposition (CVD) methods to provide shallow trench isolation regions simultaneously possessing: (1) enhanced gap filling properties; (2) enhanced bulk properties, such as but not limited to aqueous hydrofluoric acid wet chemical etch rate; and (3) attenuated surface sensitivity of the shallow trench isolation regions when formed upon thermal silicon oxide trench liner layers formed through thermal oxidation of silicon semiconductor substrates, that the present invention is more specifically directed. In a more general sense, the present invention is directed towards forming within microelectronics fabrications which are not necessarily integrated circuit microelectronics fabrications silicon oxide dielectric layers formed employing ozone-TEOS thermal chemical vapor deposition (CVD) methods, where the silicon oxide dielectric layers simultaneously possess: (1) enhanced gap filling properties; (2) enhanced bulk properties; and (3) attenuated surface sensitivity of the silicon oxide dielectic layers with respect to other microelectronics substrate layers which may include, but are not limited to, thermal silicon oxide dielectric layers formed through thermal oxidation of a silicon substrate layer.
Various methods for forming oxide isolation regions for use within integrated circuit microelectronics fabrication have been disclosed within the art of integrated circuit microelectronics fabrication.
For example, Philipossian et al., in U.S. Pat. No. 5,316,965, discloses a method for fabricating within a semiconductor integrated circuit microelectronics fabrication a silicon oxide isolation region formed of a densified and hardened silicon oxide material which in comparison with a silicon oxide material formed employing a thermal oxidation growth method exhibits an attenuated etch rate within a hydrofluoric acid etchant. The silicon oxide isolation region so formed is formed employing a nitrogen ion implant and thermal annealing of an isolation region formed from silicon oxide material formed employing a thermal chemical vapor deposition (CVD) method.
In addition, Bose et al., in U.S. Pat. No. 5,492,858, discloses a method for forming within a shallow trench within a semiconductor integrated circuit microelectronics fabrication a shallow trench isolation region of enhanced density and limited susceptibility to dishing. The shallow trench isolation region so formed is formed employing a silicon nitride trench liner layer within the trench, so that there may be employed a steam oxidation of a silicon oxide trench filling material employed when forming the shallow trench isolation region of enhanced density and limited susceptibility to dishing.
Further, Poali et al., in U.S. Pat. No. 5,641,704, discloses a method for forming shallow trench isolation regions within shallow trenches within semiconductor integrated circuit substrates, where the shallow trench isolation regions are formed with improved dielectric and gap filling properties. The shallow trench isolation regions so formed are formed employing a trilayer dielectric structure comprising a pl
Chen Ying-Ho
Jang Syun-Ming
Yu Chen-Hua
Acker Stephen B.
Jr. Carl Whitehead
Saile George O.
Stan Stephen G.
Taiwan Semiconductor Manufacturing Company
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