Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-01-08
2000-03-21
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438478, 438488, 438491, 438147, 438163, 257 72, 257 75, H01L 213205, H01L 214763
Patent
active
060402385
ABSTRACT:
A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by thermal annealing is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. The semiconductor substrate is annealed by rapid thermal annealing (RTA). Thereafter, an oxide layer is deposited overlying the silicide layer. Because the silicide layer has been annealed, silicon atoms are prevented from diffusing into the silicide layer and forming voids in the polysilicon layer. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.
REFERENCES:
patent: 4833099 (1989-05-01), Woo
patent: 5393685 (1995-02-01), Yoo et al.
patent: 5434096 (1995-07-01), Chu et al.
patent: 5472896 (1995-12-01), Chen et al.
patent: 5734179 (1998-03-01), Chang et al.
patent: 5771110 (1998-06-01), Hirano et al.
patent: 5777920 (1998-07-01), Ishigaki et al.
patent: 5837568 (1998-11-01), Yoneda et al.
patent: 5904512 (1999-05-01), Chang et al.
patent: 5915197 (1999-06-01), Yamanaka et al.
"Oxidation Phenomena of Polysilicon/Tungsten Silicide Structures" by N. Hsieh, Journal of the Electrochemical Society, Jan. 1984, p 201-5.
"Controlling Void Formation in WSi.sub.2 Polycides" by CW Koburger et al, IEEE Electron Device Letters, vol. EDL-S, No. 5, May 1984, p 166-168.
Lin Yen-Yi
Wang Jih-Hwa
Yang Chie-Ming
Ackerman Stephen B.
Bowers Charles
Kielin Erik J.
Pike Rosemary L.S.
Saile George O.
LandOfFree
Thermal annealing for preventing polycide void does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thermal annealing for preventing polycide void, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thermal annealing for preventing polycide void will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-730161