Thermal annealing for Cu seed layer enhancement

Details Thermal annealing for Cu seed layer enhancement Thermal annealing for Cu seed layer enhancement

2006-02-14

2006-02-14

Pert, Evan (Department: 2826)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S660000, C438S687000

Reexamination Certificate

active

06998337

ABSTRACT:
Semiconductor devices with highly reliable Cu interconnects exhibiting reduced resistance are formed by sequentially depositing a seed layer by PVD, depositing a conformal seed layer enhancement film by electroplating, and then thermal annealing the seed layer enhancement film in an inert or reducing atmosphere to expel impurities, enhance film conductivity, reduce film stress, increase film density, and reduce film roughness. Embodiments include single and dual Cu damascene techniques formed in dielectric layers having a dielectric constant no greater than about 3.9.

REFERENCES:
patent: 6197181 (2001-03-01), Chen
patent: 6428673 (2002-08-01), Ritzdorf et al.
patent: 6506668 (2003-01-01), Woo et al.
patent: 2002/0008036 (2002-01-01), Wang
patent: 2003/0020928 (2003-01-01), Ritzdorf et al.
patent: 2003/0066752 (2003-04-01), Ritzdorf et al.
patent: 2003/0159921 (2003-08-01), Harris et al.

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