Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-22
2004-03-30
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S901000
Reexamination Certificate
active
06713804
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a semiconductor device using an SOI (Silicon-On-Insulator) substrate, and more particularly to a structure of a semiconductor device capable of suppressing occurrence of total dose effects.
2. Description of the Background Art
FIG. 9
is a sectional view showing a structure of a conventional semiconductor device. An SOI substrate
104
has a structure in which a silicon substrate
101
, a BOX (Buried Oxide) layer
102
having a thickness of the order of several tens to several hundreds nanometers and a silicon layer
103
having a thickness of the order of several tens to several hundreds nanometers are laminated in this order. An element isolation insulating film
105
made of a silicon oxide film having a thickness of the order of several tens to several hundreds nanometers is partially formed in an upper surface of the silicon layer
103
.
In
FIG. 9
, an NMOS transistor is formed in an element forming region defined by element isolation insulating films
105
positioned on the left and in the center, respectively. More particularly, a pair of source/drain regions
106
each being of n
+
type (approximately 1×10
20
cm
−3
) are formed in the silicon layer
103
. A body region
107
of p
−
type (approximately 1×10
18
cm
−3
) is defined between the pair of source/drain regions
106
. A gate structure
111
is formed on the body region
107
. The gate structure
111
includes a gate insulating film
108
made of a silicon oxide film, a polysilicon layer
109
and a cobalt silicide layer
110
having a thickness of the order of several to several tens nanometers laminated in this order on the upper surface of the silicon layer
103
. A sidewall
112
made of a silicon oxide film is formed on a side surface of the gate structure
111
. A cobalt silicide layer
113
having a thickness of the order of several to several tens nanometers is formed on the source/drain regions
106
at an exposed part not covered by the gate structure
111
or the sidewall
112
. Moreover, in
FIG. 9
, a PMOS transistor is formed in an element forming region defined by element isolation insulating films
105
positioned in the center and on the right, respectively. More particularly, a pair of source/drain regions
114
each being of p
+
type (approximately 1×10
20
cm
−3
) are formed in the silicon layer
103
. A body region
115
of n
−
type (approximately 1×10
18
cm
−3
) is defined between the pair of source/drain regions
114
. A gate structure
119
is formed on the body region
115
. The gate structure
119
has a gate insulating film
116
made of a silicon oxide film, a polysilicon layer
117
and a cobalt silicide layer
118
having a thickness of the order of several to several tens nanometers laminated in this order on the upper surface of the silicon layer
103
. A sidewall
120
made of a silicon oxide film is formed on a side surface of the gate structure
119
. A cobalt silicide layer
121
having a thickness of the order of several to several tens nanometers is formed on the source/drain regions
114
at an exposed part not covered by the gate structure
119
or the sidewall
120
.
Further, an interlayer insulating film
122
made of a silicon oxide film having a thickness of the order of several hundreds nanometers is formed in such a manner as to cover element isolation insulating films
105
, the NMOS transistor and the PMOS transistor. An aluminum wiring
124
is formed on the interlayer insulating film
122
. The aluminum wiring
124
is connected to the cobalt silicide layer
113
or
121
through a tungsten plug
123
formed in the interlayer insulating film
122
.
FIGS. 10 and 11
are explanatory views of problems created in the conventional semiconductor device. More specifically, the drawings show the NMOS transistor in the structure shown in FIG.
9
. In the case of using LSI in space and the like, an influence exerted by total dose effects needs to be taken into consideration. The total dose effects refer to a phenomenon in which a great amount of emission of radiation such as alpha rays or gamma rays affects the operational characteristics and reliability of a semiconductor device.
Referring to
FIG. 10
, emission of radiation
130
to the semiconductor device generates a large number of hole-electron pairs along the locus of the radiation
130
by ionization it performs. Among the hole-electron pairs generated in the BOX layer
102
, the electrons of high mobility are emitted to the outside of the BOX layer
102
by an electric field. However, the holes of low mobility accumulate within the BOX layer
102
in the vicinity of the interface with respect to the silicon layer
103
.
Referring to
FIG. 11
, accumulation of the holes within the BOX layer
102
in the vicinity of the interface with respect to the silicon layer
103
causes a problem in that a threshold voltage at the MOS transistor varies due to a positive electric field resulting from the accumulated holes. Further, there arises another problem in that a channel (back channel) is formed within the body region
107
in the vicinity of the interface with respect to the BOX layer
102
so that there flows a back channel current
140
, resulting in an increase in power consumption.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of suppressing occurrence of total dose effects.
A first aspect of the present invention is directed to a semiconductor device comprising: an SOI substrate having a structure in which a supporting substrate, an insulation layer and a semiconductor layer are laminated in this order; a semiconductor element including a pair of source/drain regions formed in a main surface of the semiconductor layer, a body region defined between the pair of source/drain regions and a gate electrode formed on the main surface of the semiconductor layer with a gate insulating film interposed therebetween over the body region; and a voltage applying section applying a negative voltage which decreases with a lapse of time to the supporting substrate.
In the semiconductor device of the first aspect of the present invention, even in the case that emission of radiation causes accumulation of holes within the insulation layer in the vicinity of the interface with respect to the semiconductor layer, it is possible to cancel out a positive electric field resulting from the accumulated holes by the negative voltage applied to the supporting substrate by the voltage applying section. This, as a result, makes it possible to obtain a semiconductor device capable of suppressing occurrence of the total dose effects.
A second aspect of the present invention is directed to a semiconductor device comprising: an SOI substrate having a structure in which a supporting substrate, an insulation layer and a semiconductor layer are laminated in this order; a semiconductor element including a pair of source/drain regions formed in a main surface of the semiconductor layer, a body region defined between the pair of source/drain regions and a gate electrode formed on the main surface of the semiconductor layer with a gate insulating film interposed therebetween over the body region; and a voltage applying section applying a negative voltage which decreases with a lapse of time to the body region.
In the semiconductor device of the second aspect of the present invention, even in the case that emission of radiation causes accumulation of holes within the insulation layer in the vicinity of the interface with respect to the semiconductor layer, it is possible to cancel out a positive electric field resulting from the accumulated holes by the negative voltage applied to the body region by the voltage applying section. This, as a result, makes it possible to obtain a semiconductor device capable of suppressing occurrence of the total dose effects.
These and other objects, features, aspects and advantages of the
Hirano Yuuichi
Matsumoto Takuji
Yamaguchi Yasuo
Abraham Fetsum
Renesas Technology Corp.
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