Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
1999-05-24
2001-07-17
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C324S681000
Reexamination Certificate
active
06262589
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of inspecting a TFT (Thin-Film Transistor) array and device therefor, and, in particular, a method and device for inspecting the individual pixels constituting an LCD array.
2. Description of the Related Art
In a TFT-LCD, the TFTs are turned ON by applying voltage to their RGB inputs, and the voltage is held by the pixel capacitances by turning the TFTs OFF after the pixel capacitances have been charged. The liquid crystal shutters control the brightness by means of the voltage held on these pixel capacitances. It is therefore extremely important, for the TFT-LCD, to know the pixel capacitances. To this end, it is necessary to inspect not only the pixel capacitances before and after liquid crystal implantation, but also the parameters of the pixels constituting the TFT array i.e. whether or not the pixel capacitances are connected (open-circuit defects and short-circuit defects) and whether or not the pixel capacitance is sufficient to ensure sufficient voltage for holding the image signal during the period of a single frame.
In this inspection, as shown in
FIG. 6
, a test circuit
22
is connected to the RGB input of pixel
20
constituting the TFT array, and TFT
21
is turned ON, thereby charging pixel capacitance C
P
with voltage from test circuit
22
; TFT
21
is then turned OFF so that the voltage is held in pixel capacitance C
P
; the charge stored on pixel capacitance C
P
is ascertained from the charging current and/or held voltage when this is done. However, correctly inspecting the charge held on the pixel capacitances of the TFT array at high speed is very difficult, for the following reasons.
(1) The value of the pixel capacitance C
P
is very small, at 0.1 pF~0.2 pF.
(2) When the voltage charged on pixel capacitance C
P
is read by turning on TFT
21
, since the capacitance C
T
(~100 pF) of the tester system that is connected in parallel with pixel element C
P
and/or the pattern capacitance C
N
of the pixel (maximum 100 pF) are at least 1000 times pixel capacitance C
P
, the voltage that is read out is extremely small.
(3) Not only are the values of C
T
and C
N
large, but they have large variability and difference, unknown values for each circuit.
A prior art inspection circuit for inspecting the charge of the pixel elements of a TFT array for avoiding the problems (1) and (3) above was proposed as Laid-Open Patent Application No. H.3-200121. In this, as shown in
FIG. 7
, the source of TFT
31
is connected to pixel capacitance C
P
of the TFT array and an integration circuit
33
is connected to the drain of TFT
31
through data line
32
. Gate poser source voltage V
C
for driving this is applied to the gate of TFT
31
. In inspection circuit
34
, a switch S
1
that disconnects source voltage V
D
on data line
32
and the switch S
2
that disconnects data line
32
with integrating circuit
33
are provided; when switch S
1
is turned ON, drain power source voltage V
D
is applied to data line
32
and when TFT
31
is turned ON, the pixel capacitance C
P
of the TFT array is charged by drain power source voltage V
D
. Also, when switch S
2
is turned ON, data line
32
is connected to integrating circuit
33
and when TFT
31
is turned ON, the charge stored on TFT array pixel capacitance C
P
is applied to integrating circuit
33
.
Integrating circuit
33
comprises an operational amplifier
35
, a capacitance C
L
inserted in a feedback path connected to inverted input
37
from operational amplifier output
36
, and a reset switch S
3
connected to both ends of capacitance C
L
whereby charge stored on capacitance C
L
is discharged. The capacitance C
GD
indicated by the broken line is the stray capacitance between the gate and drain on TFT
31
; likewise, capacitance C
D
and resistance R
D
are the stray capacitance and stray resistance of the drain.
As shown in
FIG. 8
, after the rise of V
D
and turning switch S
1
ON, gate power source voltage V
G
is applied to TFT
31
from time-point T
3
to time-point T
4
, thereby turning TFT
31
ON and charging TFT array pixel capacitance C
P
with the drain power source voltage V
D
supplied through data line
32
. At time T
5
, by the drop of drain power source voltage V
D
, the charge stored on stray capacitance C
D
of data line
32
is discharged. By turning switch S
1
OFF, drain power source voltage V
D
is isolated and, by turning switch S
2
ON, data line
32
is connected to integrating circuit
33
. Also, by turning reset switch S
3
OFF, feedback capacitance C
L
is made capable of being charged. During the period necessary for charging feedback capacitance C
L
and discharging TFT array pixel capacitance C
P
i.e. from time-point T
9
to time-point T
10
, gate power source voltage V
G
is again applied to TFT
31
, thereby turning TFT
31
ON, so that the voltage on data line
32
is applied to the inverted input of operational amplifier
35
. During this period, the waveform appearing at the output of the operational amplifier drops off after charging has been saturated (due to the inverted output, this appears inverted in the Figure).
The reason that such a waveform is produced is that, although the feedback capacitance C
L
is initially charged and subsequently saturated by the voltage of both of TFT array pixel capacitance C
P
and gate/drain stray capacitance C
GD
, since the gate power source voltage V
G
drops at time-point T
10
, the voltage of the operational amplifier output is reduced by the amount of its charge (appearing inverted in the Figure), since this charge is removed from the gate/drain stray capacitance C
GD
. After the time-point T
10
, since the voltage of gate/drain stray capacitance C
GD
is removed, the voltage of the output of the operational amplifier becomes practically proportional to the voltage stored on TFT array pixel capacitance C
P
from time-point T
4
to end time T
9
i.e. the holding period. Various parameters of the pixel can then be analysed using the output voltage at this point. For example, the pixel capacitance C
P
is defined as a function of the voltage of the operational amplifier output, and the LCD leakage resistance is defined as a function of the holding period (period T
4
to T
9
).
However, with the inspection circuit of Laid-Open Patent Application No. H.3-200121 described above, as will be described, there was the problem that the construction was complicated and the inspection time-consuming, with the result that a rapid test could not be performed.
(1) The construction was complicated due to the fact that three switches were required, including the integrator and integrator reset switch.
(2) Measurement errors were considerable since an integrator of small time constant was needed, with the result that this was easily affected by noise and/or charge injected from the reset switch of the integrator.
(3) The measurement time was long since the mean value of several measurements had to be found in order to avoid the effects of noise.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the above problems of the prior art and to provide a TFT array inspection method and device whereby whether the pixels constituting a TFT array are good or not can be correctly inspected at high sped and pixel capacitance can be accurately found.
A first aspect of the invention consists in a method of TFT array inspection characterized in that the step of inspecting a pixel constituting the TFT array includes a step of: charging said pixel capacitance C
P
with a known pixel voltage V
P
and charging an additional capacitance C
T
(C
T
>>C
P
) connected in parallel with said pixel capacitance C
P
during inspection of the TFT array with a known set voltage (V
P
≠V
S
), after the charging of both of these, connecting pixel capacitance C
P
and additional capacitance C
T
in parallel, and measuring the difference voltage &Dgr;V
S
of the voltage V
a
of the additional capacitance C
T
after the parallel connection and the set vol
Asia Electronics Inc.
Karlsen Ernest
Oliff & Berridg,e PLC
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