Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2008-12-01
2011-10-25
Parker, Kenneth (Department: 2815)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S690000, C257S072000, C257S202000
Reexamination Certificate
active
08044905
ABSTRACT:
A new TFT arrangement is demonstrated, which enables prevention of TFT to be formed over a joint portion between the adjacent SOI layers prepared by the process including the separation of a thin single crystal semiconductor layer from a semiconductor wafer. The TFT arrangement is characterized by the structure where a plurality of TFTs each belonging to different pixels is gathered and arranged close to an intersection portion of a scanning line and a signal line. This structure allows the distance between regions, which are provided with the plurality of TFTs, to be extremely large compared with the distance between adjacent TFTs in the conventional TFT arrangement in which all TFTs are arranged in at a regular interval. The formation of a TFT over the joint portion can be avoided by the present arrangement, which leads to the formation of a display device with a negligible amount of display defects.
REFERENCES:
patent: 5132820 (1992-07-01), Someya et al.
patent: 5473451 (1995-12-01), Kazurov et al.
patent: 5479280 (1995-12-01), Kazurov et al.
patent: 5515187 (1996-05-01), Nakamura et al.
patent: 5532850 (1996-07-01), Someya et al.
patent: 5977940 (1999-11-01), Akiyama et al.
patent: 5986724 (1999-11-01), Akiyama et al.
patent: 6066860 (2000-05-01), Katayama et al.
patent: 6072454 (2000-06-01), Nakai et al.
patent: 6310372 (2001-10-01), Katayama et al.
patent: 6320204 (2001-11-01), Hirabayashi et al.
patent: 6323871 (2001-11-01), Fujiyoshi et al.
patent: 6335778 (2002-01-01), Kubota et al.
patent: 6403395 (2002-06-01), Hirabayashi et al.
patent: 6593626 (2003-07-01), Hirabayashi et al.
patent: 6768482 (2004-07-01), Asano et al.
patent: 7145536 (2006-12-01), Yamazaki et al.
patent: 7199808 (2007-04-01), Yo
patent: 7301517 (2007-11-01), Hebiguchi et al.
patent: 7382384 (2008-06-01), Winters et al.
patent: 7542024 (2009-06-01), Koyama
patent: 7868861 (2011-01-01), Cho et al.
patent: 7936323 (2011-05-01), Mori et al.
patent: 2002/0008240 (2002-01-01), Hirabayashi et al.
patent: 2002/0093019 (2002-07-01), Hirabayashi et al.
patent: 2002/0180902 (2002-12-01), Izumi et al.
patent: 2008/0191987 (2008-08-01), Lee et al.
patent: 64-076034 (1989-03-01), None
patent: 02-033031 (1990-03-01), None
patent: 02-234124 (1990-09-01), None
patent: 11-163363 (1999-06-01), None
patent: 2000-241829 (2000-09-01), None
patent: 2003-058080 (2003-02-01), None
Invitation to Pay Additional Fees (Application No. PCT/JP2008/071757) International Searching Authority dated Dec. 22, 2008.
Diaz José R
Parker Kenneth
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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