Testing the interrupt priority levels in a microprocessor

Details Testing the interrupt priority levels in a microprocessor Testing the interrupt priority levels in a microprocessor

2007-05-22

2007-05-22

Rinehart, Mark H. (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt prioritizing

C710S260000, C710S261000

Reexamination Certificate

active

10293901

ABSTRACT:
A method of testing the priority levels of the interrupt sources of a microprocessor having a number of interrupt sources which are each operable to execute an interrupt service routine when enabled, each interrupt source having a default priority level and an associated memory, the interrupt sources having a service order in which they are to be serviced, the method comprising the steps of: (a) sorting the interrupt sources in descending service order; (b) determining an array of priority levels to be assigned in a pre-arranged sequence to selections of interrupts in descending service order; (c) incrementing a global counter; (d) assigning the array of priority levels to a selected group of interrupts, the remainder of the interrupts assuming their pre-assigned priority level; (e) enabling all interrupts simultaneously except the interrupt source having the highest priority level so that the interrupt having the second highest priority level executes its interrupt service routine; (f) transferring the value of the global counter into the memory of the interrupt executing its interrupt service routine; (g) enabling all interrupts simultaneously including the interrupt source having the highest priority level; (h) incrementing the global counter; (i) transferring the value of the global counter into the memory of the interrupt source executing its interrupt service routine; (j) repeating steps (c) to (i) until the pre-arranged sequence is completed and (k) comparing the interrupt memory values after completion of the pre-arranged sequence with expected values and determining from the comparison whether there is an error in the priority levels of the interrupt sources.

REFERENCES:
patent: 4734882 (1988-03-01), Romagosa
patent: 5822595 (1998-10-01), Hu
patent: 5894578 (1999-04-01), Qureshi et al.
patent: 6081867 (2000-06-01), Cox
patent: 6098144 (2000-08-01), De Oliveira et al.
patent: 6167479 (2000-12-01), Hartnett et al.
patent: 6269419 (2001-07-01), Matsuyama
patent: 6499078 (2002-12-01), Beckert et al.
patent: 6581119 (2003-06-01), Maeda et al.
patent: 6618780 (2003-09-01), Popat
patent: 6813666 (2004-11-01), Joffrain
patent: 6820155 (2004-11-01), Ito
patent: 6993685 (2006-01-01), Ramaswamy et al.
patent: 2002/0112107 (2002-08-01), Joffrain

Affiliated with

Also associated with

Rating

Testing the interrupt priority levels in a microprocessor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Testing the interrupt priority levels in a microprocessor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testing the interrupt priority levels in a microprocessor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3729874