Testing semiconductor memory device having test circuit

Details Testing semiconductor memory device having test circuit Testing semiconductor memory device having test circuit

1993-05-18

1996-06-04

Beausoliel, Jr., Robert W.

Static information storage and retrieval

Read/write circuit

Testing

G11C 700, G11C 2900

Patent

active

055239773

ABSTRACT:
A semiconductor memory device having a test circuit includes voltage detection circuits (120, 220) for detecting a test mode when a voltage higher than a normal use voltage is applied to a terminal (101, 201). When one voltage detection circuit (120) detects a test mode, a voltage switching circuit (130) renders a MOS transistor (111) conductive, a resistance (115) connected in parallel to the MOS transistor is short-circuited and a voltage lower than (1/2.multidot.Vcc) is applied to a bit line voltage supply line (9). Alternatively, when the other voltage detection circuit (220) detects the test mode, a voltage switching circuit (230) renders a MOS transistor (211) conductive, a resistance (114) connected in parallel to the MOS transistor is short-circuited, and a voltage higher than (1/2.multidot.Vcc) is applied to the bit line voltage supply line. Thus, by applying a voltage higher or lower than that for normal use on a bit line, a memory cell having a small margin can be tested in a short period of time.

REFERENCES:
patent: 4553225 (1985-11-01), Ohe
patent: 4806788 (1989-02-01), Tobita
patent: 4841233 (1989-06-01), Yoshida
patent: 4860259 (1989-08-01), Tobita
patent: 4879689 (1989-11-01), Atsumi et al.
patent: 4991139 (1991-02-01), Takahashi et al.
patent: 5051995 (1991-09-01), Tobita
McAdams et al., "A 1-Mbit CMOS Dynamic RAM with Design-For Test Functions", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5 (Oct., 1986), pp. 635-642.

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