Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-07-28
2002-05-28
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185180, C365S185290
Reexamination Certificate
active
06396742
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to semiconductor memories and, in particular, to the design, operation, and testing of multilevel nonvolatile semiconductor memories.
BACKGROUND OF THE INVENTION
Testing multilevel nonvolatile memories poses new problems which are not encountered in either single-bit per cell memories or in analog memory storage architectures.
A first problem deals with detecting and screening out cells which program more than intended. To obtain the programming precision required for multilevel cells, iterative programming algorithms have been used. These algorithms execute a verify step followed by a programming pulse step if necessary (a sensing step performed during a programming algorithm is called a verify step, while a sensing step performed subsequent to the programming algorithm forms part of a read operation). The verify program iteration is repeated until the desired charge storage level in the cell is reached with the required precision. During a programming iteration, the amount of charge in the cell is incremented in small amounts so as not to overshoot the desired level. The data stored will be incorrect if a cell programs too much and overshoots the desired level. The overshoot problem poses additional detection problems when the iterative programming algorithm (technique) is used. This will be described in more detail later.
A second problem encountered in multilevel nonvolatile memories is the ability to economically test whether each memory cell in a large array of cells arranged in rows and columns receives the proper control signals for reliable multilevel operation. For example, every column and row driver circuit needs to be efficiently tested for functionality and defects such as shorted or open rows or columns need to be efficiently detected. In single-bit per cell memory, a common way to determine whether the rows and columns of cells function properly is by using such conventional programming patterns as checkerboard data patterns.
The checkerboard data pattern refers to data programmed in physical cell locations such that each programmed cell has an erased cell on adjacent orthogonal row and column locations. Programmed cells are located on diagonal adjacent locations. Defect determination is made after the data is programmed. If the data subsequently read out of the chip fails to verify to the expected checkerboard data pattern, a defect is found.
In single-bit per cell memories, the functionality determination involves only two levels per cell (i.e., programmed data level and erased data level), and the use of the checkerboard pattern is quite appropriate. In multilevel memories however, the checkerboard data pattern is insufficient to determine if the array is fully functional since the data is not restricted to just 2 levels. In multilevel operation, each memory cell will contain 2
N
levels of information, where N is the number of digital bits stored in each cell. In the examples used to describe different embodiments of this invention, 4 bits are stored per cell requiring 16 levels. Testing all 16 levels for each memory cell would fully test the multilevel functionality of the chip but would take too long and raise test and chip cost.
A third problem is the ability to properly test the cells' sensing margin. The sensing is partly accomplished by comparing a voltage value V
R
generated by the selected memory cell on a column to which it is coupled to a selected one of a plurality of reference voltage values. The sensing margin is defined as the difference between the V
R
value and the selected reference value. If the sensing margin becomes too small, the sensing circuits may not sense the data properly over the chip's specified operating temperature and power supply voltage ranges. In addition, during testing of a memory chip, voltage and/or temperature stress conditions are applied which may reduce the sensing margin in certain cells, thus allowing these cells to be identified as potentially unreliable. In multilevel memories, the separation between reference values become quite small for larger N values, e.g., for N>2. For instance, the separation between adjacent reference values which form the boundaries for each valid data range may be less than 100 mV for a 4-bit multilevel system (i.e., N=4,) but 400 mV for a 2-bit system for the same cell technology. Thus, the relatively small sensing margin for systems with N>2 requires special new testing techniques and circuitries.
Thus, new testing methodologies and circuit techniques will be described which address the above-identified problems as well as other problems encountered in testing multilevel nonvolatile memories. Also, new margin testing techniques which speed up multilevel cell testing will be described.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention, a method for testing a multilevel memory includes: performing an erase operation to place a plurality of memory cells in an erased state; programming a state of each cell in a group of the plurality of cells to within a first range of voltages; if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing; and if a state of each cell in the group of cells verifies to within the first range of voltages: applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages.
In another embodiment, the method further includes: if a state of each of one or more cells in the group of cells is programmed beyond the second range of voltages, identifying at least the one or more cells as failing.
In another embodiment, if a state of each cell in the group of cells verifies to within the first range of voltages, no verify operation is performed before or during the applying step.
In another embodiment, the first range and the second range are two of a plurality of sequentially defined voltage ranges which start with an initial range corresponding to the erased state, the first range being one of a first group of the plurality of sequentially defined voltage ranges substantially close to the initial range.
In another embodiment, each of the plurality of sequentially defined voltage ranges corresponds to one of a plurality of distributions of sensing voltages generated by the memory cells. Each of the plurality of sequentially defined voltage ranges is within a corresponding larger range of voltages, each larger range corresponding to one of 2
N
binary combinations of N bits of data capable of being stored in each cell, wherein N is a positive integer. The larger ranges are non-overlapping.
In accordance with another embodiment of the present invention, a multilevel memory has an array of erased memory cells arranged along rows and columns, each cell being capable of storing N bits of data by setting a state of each cell to within one of 2
N
voltage ranges, the cells along each row being divided into M groups, each of the M groups having a plurality of adjacent memory cells, N and M being integers greater than 1, wherein in a memory access one of a plurality of pages of memory cells in a row is selected, each page having M memory cells, one cell from each of the M groups of cells, a subset of each page of M memory cells comprising 2
N
cells. A method for testing such a multilevel memory includes: programming a state of each cell in a first group of 2
N
cells located along each column to a respective one of the 2
N
voltage ranges; and programming a state of each cell in a second group of cells comprising the 2
N
cells in the subset of a selected page along each row, each of the 2
N
cells in the subset of the selected page along each row being programmed to a respective one of the 2
N
voltage ranges.
In another embodiment, the method
Khan Sakhawat M.
Korsh George J.
Tran Hieu Van
Dinh Son T.
Gray Cary Ware & Freidenrich LLP
Silicon Storage Technology, Inc.
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