Testing methodology and apparatus for interconnects

Details Testing methodology and apparatus for interconnects Testing methodology and apparatus for interconnects

2006-05-16

2006-05-16

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C714S738000

Reexamination Certificate

active

07047458

ABSTRACT:
A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

REFERENCES:
patent: 5726991 (1998-03-01), Chen et al.
patent: 6357027 (2002-03-01), Frankowsky
patent: 6385236 (2002-05-01), Chen
patent: 6505317 (2003-01-01), Smith et al.
patent: 6609221 (2003-08-01), Coyle et al.

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