Testing method for a semiconductor memory device

Details Testing method for a semiconductor memory device Testing method for a semiconductor memory device

1992-01-08

1994-01-04

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

365177, 371 101, G11C 1300

Patent

active

052766489

ABSTRACT:
A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

REFERENCES:
patent: 4777625 (1988-10-01), Sakui et al.
patent: 4961170 (1990-10-01), Fujitsu et al.
Nikkei Electronics, Mar. 10, 1986, (No. 390), pp. 199-217.

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