Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2003-05-28
2004-08-31
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S221000, C365S189120, C365S185090
Reexamination Certificate
active
06785174
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an electronic memory device that is monolithically integrated in semiconductor and has a low pin count (LPC) interface. Particularly, but not exclusively, the present invention relates to a standard type flash memory integrated to a LPC interface block. The resulting memory device has two communication interfaces: a serial interface and a parallel interface.
The present invention further relates to a method of testing and debugging, at the on-wafer/final test stages, integrated flash memories for PCBios applications operating on a 33 MHz PCI bus, and allows a full testing flow to be carried out to detect a large number of device faults.
BACKGROUND OF THE INVENTION
The serial interface of a flash non-volatile memory has been used in applications according to precise communication protocols. On the other hand, parallel interfaces have been used almost exclusively at the device testing stage to shorten the testing time. The integrated memory device includes on its exterior twenty address pins, sixteen data pins, and a few control pins, among which are the synchronizing or clock signal CLK and a signal for setting both IC interfaces.
All the addresses and data under consideration are used in the parallel mode, and only the clock signal CLK and another four pins are needed for the serial communication protocol. The software for the testing flow, at both the on-wafer testing (Ews) and final test (assembled-device testing) stages, is currently intended for operation in the parallel mode.
However, the necessity of producing low-cost packages involves reducing the number of outer pins, thus making the provision of a new testing flow unavoidable. The outcome is that devices come equipped with just the serial communication pins in addition to the control pins required for this mode of operation. Consequently, while a standard testing flow in the parallel mode can still be carried out on-wafer, the parallel mode can not be used from the final test stage onwards.
SUMMARY OF THE INVENTION
The underlying technical problem of the present invention is to provide a new testing mode for a device having structural and functional characteristics implemented through the serial interface instead of the parallel interface. In other words, an object of the present invention is to provide a new testing procedure based on a serial communication protocol.
The present invention is based on allowing access to the test modes that are available to the manufacturer of the device by loading the data and address registers that are accessible only in the test mode.
One aspect of the present invention is directed to an electronic memory device monolithically integrated in semiconductor and comprising a serial interface having a low pin count (LPC), an array of memory cells connected to the serial interface, and row and column decode circuits connected to the array of memory cells. A bank of T-latch registers is connected to the array of memory cells to be addressed and accessed in a test mode for serially loading test data therein.
Another aspect of the present invention is directed to a method for testing a non-volatile memory device comprising a serial interface having a low pin count, an array of memory cells connected to the serial interface, and a bank of T-latch registers connected to the array of memory cells. The method comprises activating a test mode of the non-volatile memory device via an address storage block by generating a test mode signal. The address storage block is connected to the bank of T-latch registers and the array of memory cells via a first address bus. The method further includes enabling the bank of registers to serially receive a predetermined data set via an input bus connected to the serial interface, and loading test data into the bank of T-latch registers via a serial communication protocol.
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patent: 6324096 (2001-11-01), Tomita
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patent: 0651261 (1995-05-01), None
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Nadeau-Dostie et al., Serial Interfacing for Embedded-Memory Testing, IEEE Design & Test of Computers, IEEE Computers Society, Los Alamitos, US, vol. 7, No. 2, Apr. 1990, pp. 52-63, XP000159643.
Messina Marco
Perroni Maurizio
Polizzi Salvatore
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