Testing method and apparatus for dram

Details Testing method and apparatus for dram Testing method and apparatus for dram

1982-05-03

1984-08-28

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365222, G11C 1700

Patent

active

044687591

ABSTRACT:
A method for testing an MOS, dynamic random-access memory employing full capacitance dummy cells is described. During probe testing a potential higher than the reference potential is applied to the dummy cells when reading binary zeroes from the memory and a potential lower than the reference potential is applied to the dummy cells when reading binary zeroes from the memory. This testing procedure detects weak cells and amplifiers and helps present the packaging of defective parts. In addition, a simplified means for programming redundant elements is described which requires substantially less substrate area than previous methods.

REFERENCES:
patent: 4406013 (1983-09-01), Reese et al.

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