Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-07-10
2004-05-04
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000
Reexamination Certificate
active
06731551
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a semiconductor memory device, and, in particular, to testing memory using wordline testing based upon a stress signal.
2. Description of the Related Art
Modern integrated circuit devices are comprised of millions of semiconductor devices, e.g., transistors, formed above a semiconductor substrate, such as silicon. These devices are very densely packed, i.e., there is little space between them. Similarly, densely packed electrically conducting lines may also be formed in the semiconductor substrate. By forming selected electrical connections between selected semiconductor devices and selected conducting lines, circuits capable of performing complex functions may be created. For example, bits of data may be stored by providing electrical current to a plurality of bit lines and an orthogonal plurality of word lines that may be electrically coupled to one or more capacitors in a semiconductor memory.
The semiconductor memory may be a dynamic random access memory, a flash memory, and the like. The semiconductor memory typically comprises an array of memory cells, address decoding circuitry for selecting one, or a group, of the memory cells for reading or writing data, sensing circuitry for detecting the digital state of the selected memory cell or memory cells, and input/output lines to receive the sensed data and convey that information for eventual output from the semiconductor memory. In many cases, the array of memory cells will be sub-divided into several sub-arrays, or subsets, of the complete collection of memory cells. For example, a semiconductor memory having 16 megabits (2
24
bits) of storage capacity may be divided into 64 sub-arrays, each having 256K (2
18
) memory cells.
Flash memory (sometimes called “flash RAM”) is a type of non-volatile memory that can be erased and reprogrammed in units of memory called blocks. Other types of memory may be erased and rewritten in smaller units, such as units at the byte level, which is more flexible, but slower than the block operations of flash memory. Flash memory is commonly used to hold control code such as the basic input/output system (BIOS) in a personal computer. When BIOS needs to be changed (rewritten), the flash memory can be written in block (rather than byte) sizes, making it faster to update. Applications employing flash memory include digital cellular phones, digital cameras, LAN switches, computers, digital set-up boxes, embedded controllers, and other devices.
Although forming the selected electrical connections may enable the circuits to perform their intended functions, undesirable electrical connections may result in a variety of malfunctions, e.g., short circuit paths may be established. Thus, semiconductor devices, such as the capacitors in memory cells, and conducting lines, such as the input/output lines, may generally be electrically isolated. For example, to insure that devices, lines, and/or groups thereof may form the semiconductor memory are properly isolated, modern semiconductor processing involves the formation of shallow trench isolations (STI) in various regions of the substrate. These shallow trench isolations are typically formed by etching a trench in the semiconductor substrate and, thereafter, filling the trench with an isolation material, e.g., an insulator, such as silicon dioxide, silicon oxynitride, silicon nitride, or other like materials. However, it may be difficult to completely isolate the devices and/or lines. For example, defects in the semiconductor substrate or in the manufacturing process may form an undesirable conducting path between the devices and/or lines in the semiconductor memory that may cause the semiconductor memory to malfunction.
Generally, memory devices manufactured on semiconductor wafers are processed through a plurality of testing procedures. The quality of memory devices manufactured may depend upon the number of errors that are discovered while testing memory cells in the memory devices. Sections of memory are tested and areas of defects are identified for repairs and/or analysis. One method of testing memory is to provide a stress voltage signal to provide a stress condition for sections of a memory cell. For example, a stress voltage may be applied across selected rows or columns in a memory in order to test the resiliency of the components that make up the memory in the sections being tested. An example is a test to provide a positive stress voltage to alternate rows in a memory. For example, even-numbered wordlines may be grounded while the odd-numbered, opposite-row wordlines, are subjected to a positive stress voltage. Using this process, a plurality of wordlines in a memory device can be tested in a simultaneous fashion.
One problem that arises from the alternate wordline testing described above is that the stress voltage source may collapse due to shorted or repaired rows. Certain errors in the rows may cause a short to occur, shorting the stress voltage supply, thereby disrupting the testing procedure. An inability to perform efficient alternate wordline testing can cause increased costs in testing of memory and can make testing dense memory, such as flash memory, DRAMs, and other types of memory, more difficult.
SUMMARY OF THE INVENTION
In one aspect of the instant invention, a method is provided for testing a memory portion using a stress signal. The method comprises identifying a first and second portion of a memory, wherein a stress signal is to be applied to only the second portion of the memory. The first portion is isolated from exposure to a stress signal. A stress signal is provided to the second portion of said memory for testing said second portion of memory. The first portion of said memory is isolated from said stress signal.
In another aspect of the instant invention, an apparatus is provided for testing a memory portion using a stress signal. The apparatus of the present invention comprises a memory unit, a stress signal unit and a controller. The memory unit comprises a plurality of memory sectors. The stress signal unit is operatively coupled to the memory unit. The stress signal unit is adapted to provide a stress signal to the memory unit. The controller is operatively coupled with the memory unit and the stress signal unit. The controller is adapted to perform an alternate memory-sector stress signal test upon the memory unit and isolate at least one memory sector from exposure to the stress signal.
In yet another aspect of the instant invention, a system is provided for testing a memory portion using a stress signal. The system of the present invention comprises a memory unit, a stress voltage supply and an access unit. The memory unit comprises a plurality of wordlines. The stress voltage supply is operatively coupled to the memory unit. The stress voltage supply provides a stress voltage to the memory unit. The access unit is operatively coupled to the memory unit. The access unit is adapted to perform an access of a portion of the memory unit and perform an alternate wordline stress voltage test upon the memory unit while isolating at least one pre-selected wordline, by providing a stress voltage to a plurality of wordlines, in the memory unit and isolating the pre-selected wordline.
REFERENCES:
patent: 6242936 (2001-06-01), Ho et al.
patent: 6396742 (2002-05-01), Korsh et al.
patent: 6459634 (2002-10-01), Sher
Micro)n Technology, Inc.
Tran M.
Williams Morgan & Amerson P.C.
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