Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2003-05-20
2008-03-11
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
07343532
ABSTRACT:
A method of testing a memory unit in a digital circuit includes storing a test pattern on a register of the digital circuit. The register is then selected by providing an activation signal to a selection unit. The memory unit is then tested with the test pattern stored in the register.
REFERENCES:
patent: 4300234 (1981-11-01), Maruyama et al.
patent: 5432797 (1995-07-01), Takano
patent: 5889786 (1999-03-01), Shimogama
patent: 6198669 (2001-03-01), Iguchi
patent: 6779144 (2004-08-01), Hayashi et al.
patent: 2003/0021169 (2003-01-01), Beer et al.
patent: 199 51 534 (2000-05-01), None
patent: 101 35 966 (2003-02-01), None
patent: 324386 (1989-07-01), None
patent: 56140440 (1981-11-01), None
patent: 10112199 (1998-04-01), None
German Office Action dated May 24, 2002(3 pages).
Fish & Richardson P.C.
Infineon - Technologies AG
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