Testing memories

Details Testing memories Testing memories

2004-09-30

2008-10-14

Tran, Denise (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C714S718000, C714S728000

Reexamination Certificate

active

07437531

ABSTRACT:
Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo random memory addresses, and a deterministic data generation unit, such as, for example, including a state machine, to generate deterministic data to be written to the pseudo random memory addresses. Computer systems and other electronic systems including such apparatus are also disclosed.

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PI: Malgorzata Marek-Sadowska, “Sperical Pseudo-Random Pattern Testing”. Final Report 1997-1998 for Micro Report 97-109. pp. 4 pgs.
A.J. van de Gorg; “Testing Semiconductor Memories”. Chapter 5 “Psuedo-random RAM chip tests”, pp. 171-213. 1991(c).

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