Testing logic associated with numerous memory cells in the word

Details Testing logic associated with numerous memory cells in the word Testing logic associated with numerous memory cells in the word

1997-04-28

1999-11-30

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714 71, 365201, G11C 2900, G11C 700

Patent

active

059960973

ABSTRACT:
The present invention is a system and method of testing logic circuits in memory of an integrated circuit in a fraction of the time. The present invention discloses a system and method to allow testing imbedded array logic blocks in parallel, rather than sequentially. The present invention allows for the testing of multiple logic blocks associated with different memory or column locations at the same time. This technique allows for reduction in test time by a factor of X, where X is the number of rows or columns or memory cells feeding logic.

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Peter L. Gardner, Functional Memory and Its Microgramming, vol. C-20, No. 7, Jul., 1971.
J.P. Bartlett, Processing Memories, Jun. 16-18, 1970.
Sven E. Wahlstrom, Programmable Logic Arrays-Cheaper by the Millions, Dec. 11, 1967.

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