Testing for SRAM memory data retention

Details Testing for SRAM memory data retention Testing for SRAM memory data retention

2007-02-01

2009-10-20

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000, C365S202000

Reexamination Certificate

active

07606092

ABSTRACT:
A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.

REFERENCES:
patent: 5910922 (1999-06-01), Huggins et al.
patent: 5930185 (1999-07-01), Wendell
patent: 6256241 (2001-07-01), Mehalel
patent: 6813202 (2004-11-01), Iketani
patent: 2006/0187724 (2006-08-01), Pineda De Gyvez et al.

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