Testing for shorts between interconnect lines in a partially...

Details Testing for shorts between interconnect lines in a partially... Testing for shorts between interconnect lines in a partially...

2002-05-16

2004-02-03

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S725000

Reexamination Certificate

active

06687884

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to programmable logic devices (PLDs). More particularly, the invention relates to methods of testing for shorts between interconnect lines in a partially defective PLD that will prevent the PLD from being used with a specified design.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The various logic blocks are interconnected by a programmable interconnect structure that includes a large number of programmable interconnect lines (e.g., metal wires). The interconnect lines and logic blocks are interconnected using programmable interconnect points (PIPs). A PIP can be, for example, a CMOS passgate. When the passgate is turned on (i.e., the PIP is enabled), the two interconnect lines on either side of the passgate are electrically connected. When the passgate is turned off (i.e., the PIP is disabled), the two interconnect lines are isolated from each other. Thus, by controlling the values on the gate terminals of the PIPs, circuit connections can be easily made and altered.
PIPs can be implemented in many different ways. For example, a buffered PIP can be implemented as a tristate buffer. When the tristate signal is low, the buffer output is not driven, and the two interconnect lines on either side of the buffer are isolated from each other. When the tristate signal is high, one of the interconnect lines drives the other interconnect line in a unidirectional connection.
Various exemplary types of PIPs are described by Freeman in U.S. Pat. No. Re. 34,363, by Carter in U.S. Pat. Nos. 4,695,740 and 4,713,557, by Hsieh in U.S. Pat. No. 4,835,418, and by Young in U.S. Pat. No. 5,517,135, all of which are hereby incorporated by reference. Some PIPs are unidirectional and some are bidirectional. Some are buffered and some are not buffered. However, the various types of PIPs typically have this in common, that they are controlled by a single data value stored in a memory cell called a configuration memory cell.
The logic blocks and PIPs in a PLD are typically programmed (configured) by loading data from a configuration data file into thousands of configuration memory cells that define how the logic blocks and interconnect lines are configured and interconnected. In Field Programmable Gate Arrays (FPGAs), for example, each configuration memory cell is implemented as a static RAM cell.
Each PLD typically contains many thousands of configuration memory cells. A fabrication defect in any one of these memory cells makes the PLD defective for most purposes, as by the very nature of an PLD a user design can be implemented using any of the programmable resources in the device. Hence, for example, an FPGA manufacturer typically tests the functionality of each logic block and each PIP in every FPGA prior to selling the FPGA to a customer.
One type of defect that can occur is a defect in a PIP or in the memory cell controlling the PIP, such that the PIP is always enabled. In this situation, the two nets on either side of the PIP are shorted together. A PLD having this type of defect is partially defective and cannot be sold as a fully functional device.
However, if a single, specified design (i.e., a given configuration data file) will be implemented in a PLD, it is not necessary for each and every PIP in the PLD to be fully functional. It is only necessary for each PIP that affects that particular design to be functional. Any PIP actually used in routing the design must either function properly, or the defect must be such that the PIP is permanently turned on. In addition, any PIP that, if defective, will undesirably short a net in the design to some other net in the design must either function properly, or the defect must be such that the PIP is permanently turned off.
These requirements can best be understood by reviewing an example that is now explained in connection with FIG.
1
.
FIG. 1
shows a portion of a PLD that includes three logic blocks LB
1
-LB
3
, five interconnect lines IL
0
-IL
4
, and four PIPS P
1
-P
4
. Interconnect lines IL
1
-IL
3
are coupled to logic blocks LB
1
-LB
3
, respectively. Interconnect lines IL
1
-IL
3
can each be programmably coupled to interconnect line IL
0
through PIPs P
1
-P
3
, respectively. Interconnect line IL
4
can be programmably coupled to interconnect line IL
3
through PIP P
4
.
PIPS P
1
-P
4
are respectively controlled by four memory cells MC
1
-MC
4
. When the value stored in one of the memory cells is high, the passgate in the associated PIP is enabled. When the value stored in one of the memory cells is low, the interconnect lines on either side of the associated PIP are not connected together. They can be left unconnected or wired as parts of two separate circuits.
As an example, consider the case where memory cells MC
1
, MC
2
, and MC
4
each store a high value and memory cell MC
3
stores a low value. As specified by the configuration data file, PIPs P
1
and P
2
should be enabled, connecting together interconnect lines IL
1
, IL
0
, and IL
2
to form a first net. PIP P
4
should also be enabled, connecting together interconnect lines IL
3
and IL
4
to form a second net. PIP P
3
should be disabled, isolating the first and second nets from each other.
Suppose that memory cell MC
1
is defective, and the value stored in memory cell MC
1
is permanently set to a high value. Because PIP P
1
should be enabled for this design, there is no effect on the specified design. Therefore, this defect does not prevent this PLD from being used to implement the specified design. The effect is the same if there is some defect in the PIP itself that renders the PIP permanently enabled (i.e., turned on whenever the device is configured and/or power is supplied to the PLD).
However, suppose that memory cell MC
1
or PIP P
1
is defective such that PIP P
1
is permanently disabled (i.e., turned off whenever the device is configured and/or power is supplied to the PLD). The first net is incomplete, so the specified design does not work in this partially defective PLD.
Now suppose that memory cell MC
3
or PIP P
3
is defective such that PIP P
3
is permanently disabled. Because PIP P
3
should be disabled for this design, there is no effect on the specified design. Therefore, this defect does not prevent this PLD from being used to implement the specified design.
However, suppose that memory cell MC
3
or PIP P
3
is defective such that PIP P
1
is permanently enabled. The first and second nets are shorted together. The specified design does not work in this partially defective PLD.
PLDS are growing larger every year, and the larger an integrated circuit device, the more likely it is that the device will contain fabrication defects. Thus, larger PLDs are more expensive than smaller ones, not just because more silicon area is needed, but also because the likelihood of fabrication defects is higher. Thus, discarding all defective PLDs is an expensive alternative, and growing more expensive with time. However, the above examples clearly demonstrate that some partially defective PLDs can still be used in limited circumstances. A given partially defective PLD can be used with some specified designs, and not with other specified designs. Therefore, it is highly desirable to provide methods that contribute to the use of partially defective PLDs.
Clearly, if a partially defective PLD is to be used with a specified design, the PLD must be tested to see if the design will function properly in that device. One method of testing a design is simply to download the configuration data file for the design into the partially defective PLD and then operate the resulting circuit to see if it works. However, it can be a ve

Affiliated with

Also associated with

Rating

Testing for shorts between interconnect lines in a partially... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Testing for shorts between interconnect lines in a partially..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testing for shorts between interconnect lines in a partially... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3337943