Testing for operating life of a memory device with address...

Details Testing for operating life of a memory device with address... Testing for operating life of a memory device with address...

2007-08-07

2007-08-07

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S103000, C714S702000, C714S718000, C365S230030, C365S230060

Reexamination Certificate

active

10791417

ABSTRACT:
In a method and system for cycling through addresses of a memory device, a respective bit pattern comprised of a predetermined number of bits is generated for each address. The respective bit pattern for each of the addresses is cycled through with a transition of less than the predetermined number of bits for sequencing to each subsequent address. For example, the respective bit pattern for each of the addresses is cycled through in a gray code sequence. By limiting the number of transitions in the address bits, charge gain failure of a flash memory device is minimized and even may be eliminated.

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