Testing for bridge faults in the interconnect of...

Details Testing for bridge faults in the interconnect of... Testing for bridge faults in the interconnect of...

2006-12-05

2009-11-03

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07614022

ABSTRACT:
Apparatus and methods of testing for bridge faults in nets of the interconnect of a programmable integrated circuit. Each net is sourced by a function generator (e.g., a look up table) configured as a clocked shift register. For each net group, shift registers connecting nets in the group are initialized identically to one value and are initialized to a different unique value from shift registers connecting nets of other net groups. Each shift register stores one bit with a value one and zeros in all other bits. When the shift register is clocked, it provides a single one on one clock cycle and provides zeros in all other clock cycles. At the end of n clock cycles, where n is the length of the shift register, if the load on any net has a value that is different from the value provided by the net's corresponding shift register, a short is detected.

REFERENCES:
patent: 5146592 (1992-09-01), Pfeiffer et al.
patent: 5717701 (1998-02-01), Angelotti et al.
Michael R. Garey et al.; “An Application of Graph Coloring to Printed Circuit Testing”; IEEE Transactions on Circuits and Systems; vol. CAS-23; No. 10; Oct. 1976; pp. 591-599.

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