Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-05-20
2008-05-20
Tu, Christine T (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S724000
Reexamination Certificate
active
10978899
ABSTRACT:
Method and apparatus for the testing of embedded memories in integrated circuits such as programmable logic devices are disclosed. In conjunction with a partial BIST engine, an external tester provides the embedded memories with test vectors. The on-chip partial BIST engine retrieves the test vectors from the embedded memories and compares them to corresponding expected test vectors supplied by the external tester. Based upon the comparison, the on-chip partial BIST engine forms comparison results indicating whether the retrieved test vectors differ from the corresponding expected test vectors. For programmable logic devices, a full BIST engine may be configured in the integrated circuit for generating the test vectors on chip.
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Feather Robert
Nelson Michael
Vernenker Hemanshu
Lattice Semiconductor Corporation
Tu Christine T
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