Testing device and method for known good chip

Details Testing device and method for known good chip Testing device and method for known good chip

1998-10-27

2001-07-10

Karlsen, Ernest (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S754090

Reexamination Certificate

active

06259266

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a testing device, and more specifically, to a testing device for holding chips to provide electrical connection between the chips and testing apparatuses.
BACKGROUND OF THE INVENTION
Integrated circuits (IC) manufactures are constantly striving to reduce semiconductor device sizes. It has been the trend in integrated circuit (IC) technology to make small, high speed and high-density devices. Thus, the density of semiconductor devices per unit area of silicon wafer is increased. However, the high density integration of circuits makes the process more difficult, and also makes the testing methods more difficult for ensuring and promoting the qualities of the devices which are produced. For example, various testing methods are required for the chips between performing the step of dividing wafers to chips and packaging the chips completely. Wherein some testing methods are used to ensure the completed package devices conforming to functional and life-time requirements. Besides, low cost and much time efficiency for performing the various testing methods are important concerned issues.
In general, all tests performed before the chips divided from the wafers are called wafer level tests, such as CP
1
, CP
2
, WAT and so on. The WAT tests are used for sampling wafers under inspecting control in wafer process. The WAT tests, such as dielectric test, low voltage field effect transistor and high voltage field effect transistor tests (LVFET & HVFET testing), P-N junction test, OPEN/SHOT test and so on, are used for real-time controlling the qualities of wafers in processes. The CP
1
tests comprise of the OPEN/SHOT test and some gross tests, and the CP
2
tests comprise of the full function test for the chips on wafers. It is noted that the laser-repairing processes are used to promote the qualities and yields of some chips that can be amended, such as chips for memory, before performing the CP
2
tests. In addition, the tests described above within a temperature range about from −5° C./90 ° C. to 105° C. are used for eliminating some chips which will cause breakdown easily in order to ensure the chips retained all have good qualities, and can maintain a longer life-time.
The tests for testing the chips, such as memory chips, in the period between dividing the chips from the wafers and completing the packages of chips are called chip level tests. Wherein the chip level tests comprising of FT
1
, FT
2
, FT
3
and so on tests, are used for performing some tests which can't be done in wafer level tests, and for providing testing conditions much temperature differences for testing the chips, in order to eliminate some chips with defects and ensure the qualities and operating life-time of package devices satisfying the requirements. There is a burn-in process for accelerated maturing the chips between performing FT
1
tests (namely the open shot & gross tests) and FT
2
tests (namely full function test). The burn-in process is used for rapidly eliminating some devices which will breakdown prematurely, in order to ensure the packaged devices maintaining a longer life-time required. Briefly, there is a series of precondition and testing process used to promote the reliable capacities of the package devices. The relations between the developments of packaging models and testing methods are closely. Any packaging model that cannot be used for performing tests and costs much will be eliminated unless with some special functions that others cannot perform.
However, for the chips just packed to the substrate using the flip chip bumps but packaging, it's difficult to perform FT
1
, FT
2
, and FT
3
tests except the wafer level tests, such as CP
1
, CP
2
, WAT and so on. The main factor of above issues is that it is difficult to hold the fine chips and execute the sequential testing processes by using current apparatus and testing methods. It is required to develop the new testing apparatus for solving the issues above. Especially, the developments of the trays used to hold the chips, the drawer used for drawing the chips, automatic loading & unloading system, the test socket and so on, will cost much since there is not any unified standards.
Besides, the tolerance of conducting points located on chips for tests is generally below 20 &mgr;m. Relatively, the tolerance of the testing apparatus produced according to the prior technique is more than 25 &mgr;m. The tolerances caused the more incorrect judgements easily. Currently, the precisely alignment between the outer leads of the testing devices and the conducting points of the test sockets are obtained by deciding the exterior sizes and the allowed tolerance of the testing devices. However, the testing methods can't apply to test the chips without packages unless the pitches of testing points and the conducting area can overcome the tolerance caused by alignments between the testing devices and test sockets. Another solution is using a vision system added on the testing apparatus to make the alignment more precisely. In conclusion, it's essential to manufacture test sockets by using the techniques of producing chips and to test the chips by using a vision system for alignments whether the redistribution of the testing points of chips is performed, in order to avoid incorrect judgements and complete testing chips with any size. A novel method according to present invention is proposed to perform the tests for chips with flip chip bumps by using the current test apparatuses. The tests performed comprise of the FT
1
, FT
2
, and BURN-IN tests. The qualities and operating life-time for the chips located on the substrate are under control by using the method proposed according the present invention.
SUMMARY OF THE INVENTION
The prime object of the present invention is to provide a testing means for testing the chips by using the original testing apparatuses directly.
It is another object of the present invention to provide a novel testing method for testing the chips produced by chip level tests.
It is a further object of the present invention to provide a testing means to be the electrical connection interface between the chips and the testing apparatuses.
A testing means for holding chips to perform tests comprises of a plurality of inner leads for providing electrical connection for the chips with a plurality of conductive bumps. A metal layer is formed on surfaces of the plurality of inner leads for fixing the chips on the plurality of inner leads, wherein a melting point of the metal layer is below a melting point of the conductive bumps. Then, a adhesive material is pasted on a bottom surface of the plurality of inner leads for fixing the plurality of inner leads. A holding means is used to connect and hold the plurality of inner leads, and used for providing electrical connection for the plurality of inner leads.
A testing method proposed in the present invention for testing chips comprises the following steps. First, the chips are connected on a leadframe, wherein the leadframe is used for holding the chips, and the leadframe has a plurality of inner leads for electrically connecting to a testing apparatus, and the chips have a plurality of conductive bumps for connecting to the plurality of inner leads. Then, various testing steps are performed to ensure and control qualities of the chips. The chips are departed from the leadframe by a thermal process, namely the plurality of conductive bumps of the chips are departed from the plurality of inner leads of the leadframe.


REFERENCES:
patent: 4237607 (1980-12-01), Ohno
patent: 5007163 (1991-04-01), Pope et al.

Affiliated with

Also associated with

Rating

Testing device and method for known good chip does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Testing device and method for known good chip, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testing device and method for known good chip will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2469845